This contest is closed.
Patexia is looking for descriptions for connecting two semiconductor layers in a 3D integrated circuit by aligning electrical contacts between the layers so that they touch.
Submitted documents describing this system must be:
- filed or published before 05/16/2000
- not on the known references list
The entire submission must describe a connecting method with the following steps:
- creating the top layer with a semiconductor substrate and electrical contacts on the top surface
- creating holes through the semiconductor substrate, filled with electrically conductive material while still electrically insulated from the substrate, in order to connect the electrical contacts with electrical leads formed on the bottom surface
- creating a bottom semiconductor layer with the same composition, except for the holes and the electrical leads placed on the top surface
- mounting the two layers together by aligning the electrical leads into a mechanically stable connection
Figure. Diagram showing how the two layers are mounted together
|1||Is the reference either a US patent filed, a foreign patent published, or a non-patent document published before May 16th, 2000?||T/F|
|2||Does the reference generally show a method of connecting two semiconductor layers in a 3D integrated circuit by aligning electrical contacts between the layers so that they touch?||T/F|
|3||Does the reference show that the top layer has a semiconductor substrate with electrical contacts on the top surface and electrical leads on the bottom surface?||10|
|4||(3a) Does the reference further show that the electrical contacts are connected to the electrical leads through a via filled with electrically conductive material that passes through and is electrically insulated from the substrate?||20|
|5||Does reference show that the bottom layer also has a semiconductor substrate with electrical contacts on the top surface, but its electrical leads are direct on top of the electrical contacts?||20|
|6||Does the reference show that the two layers are electrically connected together by aligning the electrical leads so that they touch each other?||50|
This is a Prior Art Search contest aimed at determining if a patent idea was known and publicly available before a patent was filed.
+5 bonus points will be awarded for non-patent literature and for foreign language references.
This contest will close on Sunday, July 12th, 2015 at 11:59 PM PST.
Please review the Contest Rules. For more information on how to submit to this Contest type, please read the Intro to Prior Art Search page.
- All work must be original and prepared by a single author
- Maximum of one entry per person allowed
- Maximum length of 1,500 words
- Entries must be in English
- Ideas should be clearly expressed at a college-educated, non-expert level
- All submissions are subject to Patexia's contest legal terms
- Failure to follow these rules may lead to disqualification from the contest
- , "Sailer Philip; Singhal Piyush; et al. ""Creating 3D circuits using transferred films"". IEEE Circuits and Devices. November 1997"
- , Akasaka et al. Solid State Technology (Feb. 1989).
- , "Akasaka Y. ""Three-Dimensional IC Trends"" Proceedings of the IEEE vol. 74 No. 12 Dec. 1986 pp. 1703-1714."
- , "Hayashi Y. et al. ""Cumulatively Bonded IC (Cubic) Technology For 3D-IC Fabrication"" 8th International Workshop on Future Electron Devices Mar. 14-16 1990 pp. 85-88."
- , "Kuhn Stefan A. et al. ""Interconnect Capacitances Crosstalk and Signal Delay in Vertically Integrated Circuits"" IDEM 95-249 10.3.1 Siemens AG Corporate R&D Institute for Integrated Cirusits Fraunhofer Institute for Solid State Technology."
- , Tewksbury et al. IEEE Circuits and Devices Magazine (Sep.1989).