This contest is closed.
Patexiaseeks prior art for US Patent 6,643,713 (US ‘713) which allegedly describes a data processing system in which a DSP (digital signal processor) and a CPU (central processor unit) share the same instruction decoder and are integrated together as a single bus master.
This data processing system includes,
- a DSP
- a CPU (including an instruction decoder)
- a memory
- a single bus master
With respect to the three components mentioned above,
- the DSP and the CPU are integrated together as a single bus master
- the DSP and the CPU share the same instruction decoder
- the DSP can execute a non-recursive filter operation
- the memory stores a processing program of the CPU and the DSP
- the memory is arranged in the address space of the CPU
Figure. The configuration of a DSP/CPU integrated chip
- +5 for references that are non-patent literature
- +5 for references published in a foreign language other than English
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|1||Was the reference filed or published before Oct 5th, 1995?||T/F|
|2||Does the reference describe a system which include an integer operation digital signal processor (DSP) with a fully pipelined non-recursive filter and a central processor unit (CPU) distinct from the DSP?||5|
|3||Does the system include a common memory which stores a processing program of the CPU and the DSP, and is arranged in the address space of the CPU?||25|
|4||Does the reference confirm that the DSP and the CPU are integrated together as a single bus master?||40|
|5||Does the instruction decoder of the CPU decode instructions for both the DSP and the CPU?||30|
This is a Prior Art Search contest aimed at determining if a patent idea was known and publicly available before a patent was filed.
This contest will close on Sunday, September 14th, 2014 at 11:59 PM PST.
Please review the Contest Rules. For more information on how to submit to this Contest type, please read the Intro to Prior Art Search page.
Please review the full list of known references.
- All work must be original and prepared by a single author
- Maximum of one entry per person allowed
- Maximum length of 1,500 words
- Entries must be in English
- Ideas should be clearly expressed at a college-educated, non-expert level
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- Failure to follow these rules may lead to disqualification from the contest
- A diversificated applica tion study for memory IC Interface No. 123 Aug. 1987 (CQ Publishing).
- DSP56116 Digital Signal Processor User User's Manual issued by Motorola Inc. pp. 1-1 to 5-16 1990.
- Hitachi Single-Chip RISC Microcomputers SH7032 SH7034 Hardware Manual third edition Mar. 1964 issued by Hitachi Ltd.
- , Latest Information on GSM/Systems Terminals and Services Seminar materials Japan Industrial Technological Center May 18 and 19 1965 and Development Trend of GSM telephone Terminal Devices pp. 118-130 Japan Phillips.
- Super RISC Engine SH 7604 Hardware Manual First Edition Sep. 1994 issued by Hitachi Ltd.
- , Nikkei Electronics vol. 463 Dec. 26 1998 (Nikkei BP Corp.) Osamu Kobay ashi and others DSP which spreads its applica tion scope on the full-scale debut of 32-bit floa ting points pp. 133-146 Figs. 5 12.
- R. Meyer et al. Convolution Algorithms on DSP Processors 1991 pp. 2193-2196.
- W. Patrick Hays A Programmable Digital Signal Processor with 32b Floating Point Arithmetic 1985 IEEE International Solid-State Circuits Conference Digest of Technical Papers pp. 92-93 318.