This contest is closed.
We request previously undiscovered prior art including patents and non-patent literature (for example academic papers, technical descriptions, etc.) in English and foreign languages that can help invalidate the claims of US patent 6,787,928 (‘928) - “Integrated circuit device having pads structure formed thereon and method for forming the same.” The patent describes pads used in semiconductor packaging to connected to components on an integrated circuit.
In particular, the patent discloses an arrangement of insulator and conductor on top of the substrate of an integrated circuit. The top “pad” layer of conductor is connected to a compound structure of conducting and conduction-connection layers. This pad and compound structure are embedded within an insulator, which separates them from a lower conduction layer. This lower conduction layer is further separated from the substrate by an insulating layer. This arrangement is shown in Fig. 1 below.
Fig. 1: Integrated circuit pad structure.
If you are new, see patent and prior art basics and tips for Patexia's prior art contests, and refer to the submission notes below. The best qualifying submission is guaranteed to receive the prize. The following questions will help you understand what we are looking for in this study.
The following questions will help clarify the contest and eligible submissions. To be eligible for full prize amount, users should answer “yes” to all 8 questions and clearly where in each source justification for this source can be found.
- Was the reference published before February 26th, 2003 or described in a U.S. patent application filed in the U.S. before February 26th, 2003?
- Does the reference describe an integrated circuit having a pad structure?
- Does it describe an insulation layer formed on the substrate?
- Does it describe a lower electric conduction layer formed in the insulation layer?
- Does it describe a compound layer formed in the insulation layer?
- Does it describe a first pad layer formed on the insulation layer and coupled to this compound layer?
- Are both the first pad layer and the compound layer spaced apart from the lower electric conduction layer?
- Does it describe a second pad layer formed on the insulation layer and coupled to the lower electric conduction layer?
|1||Was the reference published before February 26th, 2003 or described in a U.S. patent application filed in the U.S. before February 26th, 2003?||0|
|2||Does the reference describe an integrated circuit having a pad structure?||0|
|3||Does it describe an insulation layer formed on the substrate?||0|
|4||Does it describe a lower electric conduction layer formed in the insulation layer?||0|
|5||Does it describe a compound layer formed in the insulation layer?||0|
|6||Does it describe a first pad layer formed on the insulation layer and coupled to this compound layer?||0|
|7||Are both the first pad layer and the compound layer spaced apart from the lower electric conduction layer?||0|
|8||Does it describe a second pad layer formed on the insulation layer and coupled to the lower electric conduction layer?||0|
- Submission deadline is February 8th, 2013 at 10:00 AM CST
- All work must be prepared by a single researcher
- The first researcher to satisfactorily respond to all 8 questions will receive the prize.
- Maximum of one entry per person allowed.
- If you were referred, the referral prize ($500) will be paid to the referring user from the total prize pool of $3,000.
- Entries must be in English.
- Please make sure to answer all the questions and explain how we can find that in the reference.
- In case you are submitting foreign references, please provide a translation of key sections.
- If your reference has already been submitted by another researcher before you or is among the known references, it will not be considered for the contest.
- Please use “Ask a Question” to post general questions or feedback about the contest to the community.
- For specific questions, you can contact us directly by email at firstname.lastname@example.org
- All submissions are subject to Patexia's contest legal terms. Failure to follow these rules may lead to disqualification from the contest.
- The simulation analysis of cross-talk behavior in SOI mixed-mode integrated circuits; Zhang Guoyan; Liao Huailin; Huang Ru; Zhang Xing; Wang Yangyuan Source: 2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443), 916-19 vol.2, 2001; ISBN-10: 0 7803 6520 8; DOI: 10.1109/ICSICT.2001.982044;
- Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits; Ming-Dou Ker; Hsin-Chin Jiang; Chyh-Yih Chang Source: Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541), 293-6, 2000; ISBN-10: 0 7803 6598 4; DOI: 10.1109/ASIC.2000.880752;
- Noise coupling in mixed-signal ASICs Schmerbeck, T.J; Source: Low-Power HF Microelectronics: A Unified Approach, 373-430, 1996; ISBN-13: 978-0-85296-874-1; DOI: 10.1049/PBCS008E_ch10;
- A highly efficient technique to suppress MOS gate-injected RF noise; Chen, Tung-Sheng; Lee, Chih-Yuan; Source: Chung Cheng Ling Hsueh Pao/Journal of Chung Cheng Institute of Technology, v 31, n 1, p 11-17, November 2002; ISSN: 02556030;
- Effects of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology; Colvin, J.T.1; Bhatia, S.S.; O, K.K.; Source: IEEE Journal of Solid-State Circuits, v 34, n 9, 1339-44, Sept. 1999; ISSN: 0018-9200; DOI: 10.1109/4.782095;
- All work must be original and prepared by a single author
- Maximum of one entry per person allowed
- Maximum length of 1,500 words
- Entries must be in English
- Ideas should be clearly expressed at a college-educated, non-expert level
- All submissions are subject to Patexia's contest legal terms
- Failure to follow these rules may lead to disqualification from the contest