Patexia. Contest

CONTEST

Competed
Prize
$25,000
DEADLINE
This contest is closed.
Winner

Gracie Allen

technology
Winner

Pavansi A

technology
Winner

Amit Aswal

technology
Winner

Simon Sunatori

technology
Winner

Yogesh Bansal

technology
Winner

sudhir G

technology
Runner Up

Roland Stumpf

technology
Runner Up

Milind Singhal

technology
Runner Up

Charu S

technology
Runner Up

Rucapillan IP

technology
Runner Up
Runner Up

Geeta Kumari

technology
Runner Up

Paton Paton

technology
Runner Up

Bimla Kumari

technology
Runner Up

Preeti S

technology
Runner Up

Mohita Agarwal

technology

Problem

Patexia seeks prior art for US Patent 6,233,174 (US ‘174) that allegedly describes a partial erasure method which reads selected cells from two different allocation groups on a nonvolatile memory into a data latch, overwrites the latched data from one of the allocations with erase data, proceeds with erasing the selected cells on the nonvolatile memory, and finally writes the latched data for both allocations back onto the nonvolatile memory.


Figure 1. Block Diagram of the Components of the Nonvolatile Memory System

Questions

  1. Was the reference filed or published before February 16th, 1998? (True/False)
  2. Does the reference describe a nonvolatile memory system which includes a controller, a data latch, and a plurality of memory cells allocated to one of two groups?
  3. Does the controller provide a partial erase operation which selects memory cells from each group, stores the data from the selected cells to the data latch, and writes erase data from an outside source onto the latched data from the second group?
  4. Does the controller continue the partial erase operation by erasing the data left on the selected memory cells from both groups, and afterwards programs the data pertaining to both groups from the data latch onto the respective memory cells?
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Questions

#QuestionValue
1Was the reference filed or published before February 16th, 1998? T/F
2Does the reference describe a nonvolatile memory system which includes a controller, a data latch, and a plurality of memory cells allocated to one of two groups? 20
3Does the controller provide a partial erase operation which selects memory cells from each group, stores the data from the selected cells to the data latch, and writes erase data from an outside source onto the latched data from the second group? 40
4Does the controller continue the partial erase operation by erasing the data left on the selected memory cells from both groups, and afterwards programs the data pertaining to both groups from the data latch onto the respective memory cells? 40

Additional Notes

Prior Art Search

This is a Prior Art Search contest aimed at determining if a patent idea was known and publicly available before a patent was filed.

This contest will close on Thursday, March 27th, 2014 at 11:59 PM PST.

This contest is subject to modified prize distribution awards:

  • the top 2 submissions will be designated as winners and receive $5,000 each
  • the next scored 4 submission will be designated as winners and receive receive $2,500 each
  • the next scored submissions (to a maximum of 10) will be designated as runner-ups and receive a minimum of $500 each

Please review the Submission Rules and Style Guidelines as well as the Style Guidelines specific to this type of contest.

Please review the full list of known references.