Mark S Graham
Examiner (ID: 16138, Phone: (571)272-4410 , Office: P/3711 )
Most Active Art Unit | 3711 |
Art Unit(s) | 3711, 3304 |
Total Applications | 3327 |
Issued Applications | 2189 |
Pending Applications | 115 |
Abandoned Applications | 723 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 17316676
[patent_doc_number] => 20210405725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => PROGRAMMABLE VOLTAGE REGULATION FOR DATA PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 17/028692
[patent_app_country] => US
[patent_app_date] => 2020-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5467
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028692
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/028692 | Programmable voltage regulation for data processor | Sep 21, 2020 | Issued |
Array
(
[id] => 17401407
[patent_doc_number] => 20220043497
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-10
[patent_title] => POWER/DATA TRANSMISSION BREAKOUT SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/987617
[patent_app_country] => US
[patent_app_date] => 2020-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7251
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 265
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16987617
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/987617 | Power/data transmission breakout system | Aug 6, 2020 | Issued |
Array
(
[id] => 17589274
[patent_doc_number] => 11327545
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-10
[patent_title] => Automated management of power distribution during a power crisis
[patent_app_type] => utility
[patent_app_number] => 16/906409
[patent_app_country] => US
[patent_app_date] => 2020-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8506
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906409
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/906409 | Automated management of power distribution during a power crisis | Jun 18, 2020 | Issued |
Array
(
[id] => 17054311
[patent_doc_number] => 20210263745
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-26
[patent_title] => FAST BOOT RESOURCE ALLOCATION FOR VIRTUAL MACHINES
[patent_app_type] => utility
[patent_app_number] => 16/801741
[patent_app_country] => US
[patent_app_date] => 2020-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10568
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801741
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/801741 | Fast boot resource allocation for virtual machines | Feb 25, 2020 | Issued |
Array
(
[id] => 16964831
[patent_doc_number] => 20210216330
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-15
[patent_title] => PERFORMANCE TUNING A DATA STORAGE SYSTEM BASED ON QUANTIFIED SCALABILITY
[patent_app_type] => utility
[patent_app_number] => 16/743352
[patent_app_country] => US
[patent_app_date] => 2020-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3853
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743352
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/743352 | Performance tuning a data storage system based on quantified scalability | Jan 14, 2020 | Issued |
Array
(
[id] => 15966463
[patent_doc_number] => 20200166983
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-28
[patent_title] => METHOD AND APPARATUS FOR ANALYZING SENSOR DATA
[patent_app_type] => utility
[patent_app_number] => 16/691147
[patent_app_country] => US
[patent_app_date] => 2019-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9942
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16691147
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/691147 | Method and apparatus for analyzing sensor data | Nov 20, 2019 | Issued |
Array
(
[id] => 15622221
[patent_doc_number] => 20200081515
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-12
[patent_title] => SYSTEM ON CHIP CONTROLLING MEMORY POWER USING HANDSHAKE PROCESS AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/670026
[patent_app_country] => US
[patent_app_date] => 2019-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7686
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670026
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/670026 | System on chip controlling memory power using handshake process and operating method thereof | Oct 30, 2019 | Issued |
Array
(
[id] => 17528332
[patent_doc_number] => 11301016
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-12
[patent_title] => Computing devices and methods of allocating power to plurality of cores in each computing device
[patent_app_type] => utility
[patent_app_number] => 16/518421
[patent_app_country] => US
[patent_app_date] => 2019-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5743
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518421
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/518421 | Computing devices and methods of allocating power to plurality of cores in each computing device | Jul 21, 2019 | Issued |
Array
(
[id] => 15042307
[patent_doc_number] => 20190332158
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-31
[patent_title] => DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 16/508916
[patent_app_country] => US
[patent_app_date] => 2019-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12508
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16508916
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/508916 | DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS | Jul 10, 2019 | Abandoned |
Array
(
[id] => 15043011
[patent_doc_number] => 20190332510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-31
[patent_title] => DETECTING A CHANGE TO SYSTEM MANAGEMENT MODE BIOS CODE
[patent_app_type] => utility
[patent_app_number] => 16/503887
[patent_app_country] => US
[patent_app_date] => 2019-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6814
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503887
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/503887 | Detecting a change to system management mode bios code | Jul 4, 2019 | Issued |
Array
(
[id] => 17893890
[patent_doc_number] => 11456883
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-27
[patent_title] => Multiple phase pulse power in a network communications system
[patent_app_type] => utility
[patent_app_number] => 16/380954
[patent_app_country] => US
[patent_app_date] => 2019-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 19
[patent_no_of_words] => 7203
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380954
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/380954 | Multiple phase pulse power in a network communications system | Apr 9, 2019 | Issued |
Array
(
[id] => 15327969
[patent_doc_number] => 20200004314
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-02
[patent_title] => AUTOMATIC ENERGY DESIGN AND MANAGEMENT SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/380825
[patent_app_country] => US
[patent_app_date] => 2019-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11400
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380825
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/380825 | AUTOMATIC ENERGY DESIGN AND MANAGEMENT SYSTEM | Apr 9, 2019 | Abandoned |
Array
(
[id] => 15027013
[patent_doc_number] => 20190324511
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-24
[patent_title] => CONTROLLER, CONTROL METHOD, AND CONTROL PROGRAM
[patent_app_type] => utility
[patent_app_number] => 16/372176
[patent_app_country] => US
[patent_app_date] => 2019-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8331
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16372176
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/372176 | CONTROLLER, CONTROL METHOD, AND CONTROL PROGRAM | Mar 31, 2019 | Abandoned |
Array
(
[id] => 17408656
[patent_doc_number] => 11249536
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-15
[patent_title] => Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling
[patent_app_type] => utility
[patent_app_number] => 16/222381
[patent_app_country] => US
[patent_app_date] => 2018-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 9691
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222381
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/222381 | Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling | Dec 16, 2018 | Issued |
Array
(
[id] => 14223069
[patent_doc_number] => 20190123919
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-25
[patent_title] => SWITCHING DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/220891
[patent_app_country] => US
[patent_app_date] => 2018-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15283
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220891
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/220891 | SWITCHING DEVICE | Dec 13, 2018 | Abandoned |
Array
(
[id] => 17924373
[patent_doc_number] => 11467620
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-10-11
[patent_title] => Architecture and methodology for tuning clock phases to minimize latency in a serial interface
[patent_app_type] => utility
[patent_app_number] => 16/217503
[patent_app_country] => US
[patent_app_date] => 2018-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7886
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16217503
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/217503 | Architecture and methodology for tuning clock phases to minimize latency in a serial interface | Dec 11, 2018 | Issued |
Array
(
[id] => 14443041
[patent_doc_number] => 20190179393
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => ELECTRONIC APPARATUS, CONTROL METHOD IN ELECTRONIC APPARATUS, AND APPARATUS
[patent_app_type] => utility
[patent_app_number] => 16/199826
[patent_app_country] => US
[patent_app_date] => 2018-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7320
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16199826
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/199826 | Electronic apparatus, control method in electronic apparatus, and apparatus | Nov 25, 2018 | Issued |
Array
(
[id] => 16705964
[patent_doc_number] => 10955893
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-23
[patent_title] => Dynamic voltage margin recovery
[patent_app_type] => utility
[patent_app_number] => 16/159821
[patent_app_country] => US
[patent_app_date] => 2018-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 9138
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159821
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/159821 | Dynamic voltage margin recovery | Oct 14, 2018 | Issued |
Array
(
[id] => 17846433
[patent_doc_number] => 11435802
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-06
[patent_title] => Work load scheduling for multi core systems with under-provisioned power delivery
[patent_app_type] => utility
[patent_app_number] => 15/968348
[patent_app_country] => US
[patent_app_date] => 2018-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 23
[patent_no_of_words] => 6664
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15968348
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/968348 | Work load scheduling for multi core systems with under-provisioned power delivery | Apr 30, 2018 | Issued |
Array
(
[id] => 16651706
[patent_doc_number] => 10928879
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-23
[patent_title] => Architecture for improving reliability of mult-server system
[patent_app_type] => utility
[patent_app_number] => 16/097125
[patent_app_country] => US
[patent_app_date] => 2017-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3968
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 917
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16097125
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/097125 | Architecture for improving reliability of mult-server system | Sep 13, 2017 | Issued |