Richard M Camby

Array ( [id] => 3997480 [patent_doc_number] => 05961649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio' [patent_app_type] => 1 [patent_app_number] => 8/985391 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5251 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961649.pdf [firstpage_image] =>[orig_patent_app_number] => 985391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057762 [patent_doc_number] => 05996074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'In-box configuration apparatus for a computer system' [patent_app_type] => 1 [patent_app_number] => 8/971242 [patent_app_country] => US [patent_app_date] => 1997-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2009 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996074.pdf [firstpage_image] =>[orig_patent_app_number] => 971242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4240344 [patent_doc_number] => 06012142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Methods for booting a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/970794 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 10939 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012142.pdf [firstpage_image] =>[orig_patent_app_number] => 970794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4022721 [patent_doc_number] => 05987620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method and apparatus for a self-timed and self-enabled distributed clock' [patent_app_type] => 1 [patent_app_number] => 8/969866 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12506 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987620.pdf [firstpage_image] =>[orig_patent_app_number] => 969866 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915583 [patent_doc_number] => 05944820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Modifiable partition boot record for a computer memory device' [patent_app_type] => 1 [patent_app_number] => 8/951135 [patent_app_country] => US [patent_app_date] => 1997-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1842 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944820.pdf [firstpage_image] =>[orig_patent_app_number] => 951135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4156295 [patent_doc_number] => 06122733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method and apparatus for updating a basic input/output system' [patent_app_type] => 1 [patent_app_number] => 8/941535 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6913 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122733.pdf [firstpage_image] =>[orig_patent_app_number] => 941535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4037123 [patent_doc_number] => 05968180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Data capture circuit for asynchronous data transfer' [patent_app_type] => 1 [patent_app_number] => 8/940626 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4177 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968180.pdf [firstpage_image] =>[orig_patent_app_number] => 940626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915798 [patent_doc_number] => 05944834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Timing analysis method for PLLS' [patent_app_type] => 1 [patent_app_number] => 8/938659 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3705 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944834.pdf [firstpage_image] =>[orig_patent_app_number] => 938659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4007959 [patent_doc_number] => 05920690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Method and apparatus for providing access protection in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/907980 [patent_app_country] => US [patent_app_date] => 1997-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2708 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920690.pdf [firstpage_image] =>[orig_patent_app_number] => 907980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4041907 [patent_doc_number] => 05903719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Emulator apparatus and emulation method for efficiently analyzing program faults' [patent_app_type] => 1 [patent_app_number] => 8/905350 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4252 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903719.pdf [firstpage_image] =>[orig_patent_app_number] => 905350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3924249 [patent_doc_number] => 05938777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Cycle list based bus cycle resolution checking in a bus bridge verification system' [patent_app_type] => 1 [patent_app_number] => 8/904191 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9385 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938777.pdf [firstpage_image] =>[orig_patent_app_number] => 904191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3971141 [patent_doc_number] => 05991896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method and apparatus for protecting an electronic system from erroneous operation due to static electricity' [patent_app_type] => 1 [patent_app_number] => 8/899809 [patent_app_country] => US [patent_app_date] => 1997-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1963 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991896.pdf [firstpage_image] =>[orig_patent_app_number] => 899809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4036565 [patent_doc_number] => 05968142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Behavior control of apparatus having a physically-removable resource' [patent_app_type] => 1 [patent_app_number] => 8/887317 [patent_app_country] => US [patent_app_date] => 1997-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3073 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968142.pdf [firstpage_image] =>[orig_patent_app_number] => 887317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4036478 [patent_doc_number] => 05968136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Apparatus and method for secure device addressing' [patent_app_type] => 1 [patent_app_number] => 8/869659 [patent_app_country] => US [patent_app_date] => 1997-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6481 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968136.pdf [firstpage_image] =>[orig_patent_app_number] => 869659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3923135 [patent_doc_number] => 05928336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'PC card and peripheral device' [patent_app_type] => 1 [patent_app_number] => 8/856567 [patent_app_country] => US [patent_app_date] => 1997-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5791 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/928/05928336.pdf [firstpage_image] =>[orig_patent_app_number] => 856567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3944939 [patent_doc_number] => 05935222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Arrangement with a signal processing connection and a functional unit' [patent_app_type] => 1 [patent_app_number] => 8/793192 [patent_app_country] => US [patent_app_date] => 1997-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1728 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935222.pdf [firstpage_image] =>[orig_patent_app_number] => 793192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4240474 [patent_doc_number] => 06012151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Information processing apparatus and distributed processing control method' [patent_app_type] => 1 [patent_app_number] => 8/839911 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 58 [patent_no_of_words] => 16825 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012151.pdf [firstpage_image] =>[orig_patent_app_number] => 839911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3923689 [patent_doc_number] => 05938740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Programmable peripheral control device for controlling peripherals of a computer system' [patent_app_type] => 1 [patent_app_number] => 8/837535 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2581 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938740.pdf [firstpage_image] =>[orig_patent_app_number] => 837535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3969350 [patent_doc_number] => 05948113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'System and method for centrally handling runtime errors' [patent_app_type] => 1 [patent_app_number] => 8/844391 [patent_app_country] => US [patent_app_date] => 1997-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9577 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948113.pdf [firstpage_image] =>[orig_patent_app_number] => 844391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4076682 [patent_doc_number] => 05896550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Direct memory access controller with full read/write capability' [patent_app_type] => 1 [patent_app_number] => 8/825661 [patent_app_country] => US [patent_app_date] => 1997-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896550.pdf [firstpage_image] =>[orig_patent_app_number] => 825661 [rel_patent_id] =>[rel_patent_doc_number] =>)