Search

Stephen Francis Gerrity

Examiner (ID: 145, Phone: (571)272-4460 , Office: P/3721 )

Most Active Art Unit
3721
Art Unit(s)
3721, 2411, 2402, 3722, 2852, 3727, 3405, 3731
Total Applications
3621
Issued Applications
2881
Pending Applications
197
Abandoned Applications
504

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11473933 [patent_doc_number] => 20170060716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'PERSISTENT COMMAND PARAMETER TABLE FOR PRE-SILICON DEVICE TESTING' [patent_app_type] => utility [patent_app_number] => 15/349418 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4743 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349418 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/349418
Persistent command parameter table for pre-silicon device testing Nov 10, 2016 Issued
Array ( [id] => 11891145 [patent_doc_number] => 09761712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'Vertical transistors with merged active area regions' [patent_app_type] => utility [patent_app_number] => 15/338867 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7396 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338867 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338867
Vertical transistors with merged active area regions Oct 30, 2016 Issued
Array ( [id] => 12153841 [patent_doc_number] => 20180025105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'SIMULATING REFERENCE VOLTAGE RESPONSE IN DIGITAL SIMULATION ENVIRONMENTS' [patent_app_type] => utility [patent_app_number] => 15/215757 [patent_app_country] => US [patent_app_date] => 2016-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15215757 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/215757
Simulating reference voltage response in digital simulation environments Jul 20, 2016 Issued
Array ( [id] => 12333273 [patent_doc_number] => 09947088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Evaluation condition setting method of semiconductor device, and evaluation condition setting apparatus [patent_app_type] => utility [patent_app_number] => 15/215888 [patent_app_country] => US [patent_app_date] => 2016-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5236 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15215888 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/215888
Evaluation condition setting method of semiconductor device, and evaluation condition setting apparatus Jul 20, 2016 Issued
Array ( [id] => 11086673 [patent_doc_number] => 20160283639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'Semiconductor Device Design Methods and Conductive Bump Pattern Enhancement Methods' [patent_app_type] => utility [patent_app_number] => 15/174795 [patent_app_country] => US [patent_app_date] => 2016-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5707 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15174795 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/174795
Semiconductor device design methods and conductive bump pattern enhancement methods Jun 5, 2016 Issued
Array ( [id] => 12146863 [patent_doc_number] => 09881116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'Restricted region transform method and restricted region transform device' [patent_app_type] => utility [patent_app_number] => 15/152679 [patent_app_country] => US [patent_app_date] => 2016-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3598 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15152679 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/152679
Restricted region transform method and restricted region transform device May 11, 2016 Issued
Array ( [id] => 12101276 [patent_doc_number] => 09858371 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-02 [patent_title] => 'Method and system for generating post-silicon validation tests' [patent_app_type] => utility [patent_app_number] => 15/149304 [patent_app_country] => US [patent_app_date] => 2016-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5521 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15149304 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/149304
Method and system for generating post-silicon validation tests May 8, 2016 Issued
Array ( [id] => 12167770 [patent_doc_number] => 09886539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-06 [patent_title] => 'Designing circuits using pseudohierarchy' [patent_app_type] => utility [patent_app_number] => 15/099317 [patent_app_country] => US [patent_app_date] => 2016-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9034 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15099317 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/099317
Designing circuits using pseudohierarchy Apr 13, 2016 Issued
Array ( [id] => 12167768 [patent_doc_number] => 09886537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-06 [patent_title] => 'Method of supporting design, computer product, and semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 15/096774 [patent_app_country] => US [patent_app_date] => 2016-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 9374 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15096774 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/096774
Method of supporting design, computer product, and semiconductor integrated circuit Apr 11, 2016 Issued
Array ( [id] => 11043311 [patent_doc_number] => 20160240267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'PERSISTENT COMMAND PARAMETER TABLE FOR PRE-SILICON DEVICE TESTING' [patent_app_type] => utility [patent_app_number] => 15/073221 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4715 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073221 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073221
Persistent command parameter table for pre-silicon device testing Mar 16, 2016 Issued
Array ( [id] => 11882197 [patent_doc_number] => 09753363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-05 [patent_title] => 'Scanner based optical proximity correction system and method of use' [patent_app_type] => utility [patent_app_number] => 15/041312 [patent_app_country] => US [patent_app_date] => 2016-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10715 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15041312 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/041312
Scanner based optical proximity correction system and method of use Feb 10, 2016 Issued
Array ( [id] => 11524275 [patent_doc_number] => 09607684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Circuit-level abstraction of multigate devices using two-dimensional technology computer aided design' [patent_app_type] => utility [patent_app_number] => 14/993221 [patent_app_country] => US [patent_app_date] => 2016-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14993221 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/993221
Circuit-level abstraction of multigate devices using two-dimensional technology computer aided design Jan 11, 2016 Issued
Array ( [id] => 12201687 [patent_doc_number] => 09904753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Methods for designing a layout of a semiconductor device including at least one risk via' [patent_app_type] => utility [patent_app_number] => 14/991330 [patent_app_country] => US [patent_app_date] => 2016-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 15517 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14991330 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/991330
Methods for designing a layout of a semiconductor device including at least one risk via Jan 7, 2016 Issued
Array ( [id] => 11848217 [patent_doc_number] => 09735781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Physically unclonable camouflage structure and methods for fabricating same' [patent_app_type] => utility [patent_app_number] => 14/985270 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 48 [patent_no_of_words] => 19369 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14985270 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/985270
Physically unclonable camouflage structure and methods for fabricating same Dec 29, 2015 Issued
Array ( [id] => 12967303 [patent_doc_number] => 09875329 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-23 [patent_title] => Method and system for import of mask layout data to a target system [patent_app_type] => utility [patent_app_number] => 14/983288 [patent_app_country] => US [patent_app_date] => 2015-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14983288 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/983288
Method and system for import of mask layout data to a target system Dec 28, 2015 Issued
Array ( [id] => 11510311 [patent_doc_number] => 09601477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Integrated circuit having spare circuit cells' [patent_app_type] => utility [patent_app_number] => 14/974367 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7699 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14974367 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/974367
Integrated circuit having spare circuit cells Dec 17, 2015 Issued
Array ( [id] => 11321000 [patent_doc_number] => 09519744 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-13 [patent_title] => 'Merging of storage elements on multi-cycle signal distribution trees into multi-bit cells' [patent_app_type] => utility [patent_app_number] => 14/960812 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14960812 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/960812
Merging of storage elements on multi-cycle signal distribution trees into multi-bit cells Dec 6, 2015 Issued
Array ( [id] => 12196109 [patent_doc_number] => 09899852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Power bank charging system' [patent_app_type] => utility [patent_app_number] => 14/953278 [patent_app_country] => US [patent_app_date] => 2015-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2090 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14953278 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/953278
Power bank charging system Nov 26, 2015 Issued
Array ( [id] => 12215368 [patent_doc_number] => 09912188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Charging device' [patent_app_type] => utility [patent_app_number] => 14/952818 [patent_app_country] => US [patent_app_date] => 2015-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3497 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14952818 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/952818
Charging device Nov 24, 2015 Issued
Array ( [id] => 11346320 [patent_doc_number] => 09530734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Enforcement of semiconductor structure regularity for localized transistors and interconnect' [patent_app_type] => utility [patent_app_number] => 14/949761 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 10371 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14949761 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/949761
Enforcement of semiconductor structure regularity for localized transistors and interconnect Nov 22, 2015 Issued
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