Agilent Technologies introduces industry's first reference clock multiplier for receiver test

Agilent Technologies Inc. today announced the industry's first reference clock multiplier. The Agilent N4880A reference clock multiplier enables R&D and test engineers to lock the pattern generator clock of the J-BERT N4903B and the ParBERT 81250A to reference clocks from the system under test. The new solution supports multiple reference clock rates ranging from 19 to 100 MHz for receiver test applications such as PCIe® 1.x, 2.x and 3.0 main boards, MIPI M-PHY devices and UHS-II host devices. The use of the reference clock multiplier significantly simplifies the receiver test setup, helping R&D and test teams to accurately characterize and verify standard compliance under easy to reproduce test conditions. With common reference clock architectures, where the host cannot run on an external reference clock, it is necessary to lock the generated stressed-pattern signal to the reference clock from the receiver under test. That's because the receiver under test also derives its sampling clock from this reference clock. Not locking the stressed pattern generator to the same reference clock would lead to wrong and non-reproducible jitter-tolerance test results.