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Patexia Research
Patent No. US 08207881
Issue Date Jun 26, 2012
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Patent 08207881 - High speed low voltage flash > Claims

  • 1. An analogue to digital converter comprising:nfirst and second sets of ordered nodes, each first node having a corresponding second node;for each first node, a respective first resistor and current source pair, the resistor of each pair being coupled between the first node and a first converter input and the current source of each pair being coupled to the respective first node;for each second node, a respective second resistor and current source pair, the resistor of each pair being coupled between the second node and a second converter input and the current source of each pair being coupled to the respective second node; anda plurality of first comparators, each first comparator having its first input connected to a first node and its second input connected to the corresponding second node;wherein each of the first resistor and current source pairs are configured so as to provide an orderly progression of voltages at the first nodes and each of the second resistor and current source pairs are configured so as to provide an orderly progression of voltages at the second nodes.
    • 2. An analogue to digital converter as claimed in claim 1, wherein the voltages at a first subset of the first nodes form an orderly progression of voltages between the voltage at the first converter input and an upper supply voltage and the voltages at a second subset of the first nodes form an orderly progression of voltages between the voltage at the first converter input and a lower supply voltage.
      • 3. An analogue to digital converter as claimed in claim 2, wherein the voltages at a first subset of the second nodes form an orderly progression of voltages between the voltage at the second converter input and the upper supply voltage and the voltages at a second subset of the second nodes form an orderly progression of voltages between the voltage at the second converter input and the lower supply voltage.
        • 4. An analogue to digital converter as claimed in claim 3, wherein the respective current sources of the first subset of first nodes and the second subset of second nodes are sinking current sources, and the respective current sources of the second subset of first nodes and the first subset of second nodes are sourcing current sources.
    • 5. An analogue to digital converter as claimed in claim 1, further comprising a second comparator having its first input connected to the first converter input and its second input connected to the second converter input.
      • 6. An analogue to digital converter as claimed in claim 5, wherein the first and second sets of nodes each have N nodes and the total number of first and second comparators is N, each comparator having its first and second inputs connected such that a comparator having its first input connected to the node at position x in the first set has its second input connected to the node at position N+1−x in the second set, where x=1 at the nodes adjacent to the first and second converter inputs and x=N at the nodes at the terminating ends of the first and second ordered sets of nodes, the remaining nodes in each set being arranged in successive order therebetween.
    • 7. An analogue to digital converter as claimed in claim 1, wherein the voltages at the first nodes form an orderly progression of voltages between the voltage at the first converter input and an upper supply voltage and the voltages at the second nodes form an orderly progression of voltages between the voltage at the second converter input and an upper supply voltage.
      • 8. An analogue to digital converter as claimed in claim 7, wherein the respective current sources of the first and second nodes are sourcing current sources.
      • 11. An analogue to digital converter as claimed in claim 7, further comprising a third comparator having its first input connected to the first converter input and its second input connected to the last node in the ordered set of second nodes.
      • 12. An analogue to digital converter as claimed in claim 7, further comprising a fourth comparator having its second input connected to the second converter input and its first input connected to the last node in the ordered set of first nodes.
    • 9. An analogue to digital converter as claimed in claim 1, wherein the voltages at the first nodes form an orderly progression of voltages between the voltage at the first converter input and a lower supply voltage and the voltages at the second nodes form an orderly progression of voltages between the voltage at the second converter input and a lower supply voltage.
      • 10. An analogue to digital converter as claimed in claim 9, wherein the respective current sources of the first and second nodes are sinking current sources.
    • 13. An analogue to digital converter as claimed in claim 1, wherein the first and second converter inputs are a pair of differential inputs.
    • 14. An analogue to digital converter as claimed in claim 1, wherein the first converter input voltage is a single-ended input voltage and the second converter input voltage is synthesised from the first converter input voltage so as to maintain the midpoint voltage between the two converter input voltages at the midpoint voltage between the upper and lower supply voltages supplied to the analogue to digital converter.
    • 15. An analogue to digital converter as claimed in claim 1, wherein each said resistor has the same nominal resistance and each said current source is configured to provide a predetermined multiple of a fixed current.
      • 16. An analogue to digital converter as claimed in claim 15, wherein the predetermined multiples are chosen such that, in the absence of input voltages at the first and second converter inputs, the voltages on the nodes in each of the first and second sets form a linear progression.
      • 17. An analogue to digital converter as claimed in claim 15, wherein the predetermined multiples are chosen such that, in the absence of input voltages at the first and second converter inputs, the voltages on the nodes in each of the first and second sets form a logarithmic progression.
    • 18. An analogue to digital converter as claimed in claim 1, wherein the first and second converter input voltages are biased such that the midpoint voltage between the two converter input voltages is maintained at the midpoint voltage between upper and lower supply voltages supplied to the analogue to digital converter.
    • 19. An electronic device comprising an analogue to digital converter as claimed in claim 1.
    • 20. An integrated circuit comprising an analogue to digital converter as claimed in claim 1.
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