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Patexia Research
Patent No. US 09455675
Issue Date Sep 27, 2016
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Patent 09455675 - Amplifier and amplification method > Claims

  • 1. An amplifier comprising:na biasing unit, configured to generate a bias current which is independent of the power supply, so as to increase power supply rejection ratio;an amplifying unit connected to the biasing unit and configured to receive an input voltage and generate an amplified voltage based on the biasing current;a Schmitt trigger connected to the amplifying unit and configured to generate and output a modified voltage;wherein the biasing unit comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a current mirror, a first resistor; whereina source of the first NMOS transistor is connected to a ground, a gate of the first NMOS transistor is connected to both the first resistor and a source of the second NMOS transistor, a drain of the first NMOS transistor is connected to both a gate of the second NMOS transistor and a first port of the current mirror;a drain of the second NMOS transistor is connected to a second port of the current mirror;a source of the third PMOS transistor is connected to a second voltage supply, and a drain of the third PMOS transistor is configured to output the biasing current.
    • 2. The amplifier of claim 1, further comprisingnat least one inverter connected to the Schmitt trigger and configured to generate an output voltage by buffering the modified voltage.
    • 3. The amplifier of claim 1, whereinnthe current source comprises a fourth PMOS transistor and a fifth PMOS transistor, wherein the first port the current mirror comprises a drain of the fifth PMOS transistor, the second port of the current mirror comprises a drain of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to a gate of the fifth PMOS transistor, both sources of the fourth PMOS transistor and the fifth PMOS transistor are connected to the positive power supply.
    • 4. The amplifier of claim 1, further comprising a sixth PMOS transistor, a first inverter and a second inverter both connected to the Schmitt trigger and configured to generate an output voltage by buffering the modified voltage, wherein a source of the sixth PMOS transistor is connected to the positive power supply, a gate of the sixth PMOS transistor is connected to the gate of the third PMOS transistor, a drain of the sixth PMOS transistor is connected to the second inverter and is configured to provide a power supply for the second inverter.
      • 5. The amplifier of claim 4, wherein the first inverter further comprises a seventeenth MOS transistor and an eighteenth MOS transistor,nwherein a source of the seventeenth PMOS transistor is connected to the third resistor, both gates of the seventeenth PMOS transistor and the eighteenth NMOS transistor are connected to the drain of the twelfth NMOS transistor, a drain of the seventeenth PMOS transistor is connected to a drain of the eighteenth NMOS transistor, a source of the eighteenth NMOS transistor is connected to the ground.
        • 6. The amplifier of claim 5, wherein the second inverter further comprises a nineteenth PMOS transistor and an twentieth NMOS transistor,nwherein a source of the nineteenth PMOS transistor is connected to the second resistor, both gates of the nineteenth PMOS transistor and the twentieth MOS transistor are connected to the drain of the seventeenth PMOS transistor, a drain of the nineteenth PMOS transistor is connected to a drain of the twentieth NMOS transistor, a source of the twentieth NMOS transistor is connected to the ground.
    • 7. The amplifier of claim 1, wherein the amplifying unit comprises a seventh PMOS transistor, an eighth NMOS transistor, a first capacitor and a fifth resistor; whereinnboth gates of the seventh PMOS transistor and the eighth NMOS transistor are configured to receive an input voltage via the first capacitor; both drains of the seventh PMOS transistor and the eighth NMOS transistor are connected to the Schmitt trigger, and the source of the seventh PMOS transistor is connected to the drain of the third PMOS transistor via a second resistor, a third resistor and a fourth resistor in serials, a source of the eighth NMOS transistor is connected to the ground; wherein the fifth resistor is connected between the first capacitor and the drain of the eighth NMOS transistor.
      • 8. The amplifier of claim 7, wherein the amplifying unit further comprises a ninth PMOS transistor, a tenth NMOS transistor, and a second capacitor, and a sixth resistor; whereinna source of the ninth PMOS transistor is connected to the source of the seventh PMOS transistor, a gate of the ninth PMOS transistor is connected to the ground via the second capacitor, a drain the ninth PMOS transistor is connected to both a gate and a drain of the tenth NMOS transistor; a source of the tenth NMOS transistor is connected to the ground; wherein the sixth resistor is connected between the second capacitor and the drain of the eighth NMOS transistor.
      • 9. The amplifier of claim 7, wherein the Schmitt trigger comprises an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, and a fifteenth PMOS transistor,nwherein gates of all of the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth PMOS transistor and the fourteenth PMOS transistor are connected to the drain of the seventh PMOS transistor;a source of the fourteenth PMOS transistor is connected to the third resistor, a drain of the fourteenth PMOS transistor is connected to a source of the thirteenth PMOS transistor;a drain of the thirteenth PMOS transistor is connected to a drain of the twelfth NMOS transistor, a source of the twelfth NMOS transistor is connected to a drain of the eleventh NMOS transistor, a source of the eleventh NMOS transistor is connected to the ground;a source of the fifteenth PMOS transistor is connected to the source of the thirteenth PMOS transistor, a gate of the fifteenth PMOS transistor is connected to the drain of the thirteenth PMOS transistor, a drain of the fifteenth PMOS transistor is connected to the ground.
        • 10. The amplifier of claim 9, wherein the Schmitt trigger further comprises a sixteenth NMOS transistor, whereinna source of the sixteenth NMOS transistor is connected to the source of the twelfth NMOS transistor, a gate of the sixteenth NMOS transistor is connected to the gate of the fifteenth PMOS transistor, a drain of the sixteenth NMOS transistor is connected to the third resistor.
      • 11. The amplifier of claim 7, wherein the Schmitt trigger comprises an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, and a sixteenth NMOS transistor,nwherein gates of all of the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth PMOS transistor and the fourteenth PMOS transistor are connected to the drain of the seventh PMOS transistor;a source of the fourteenth PMOS transistor is connected to the third resistor, a drain of the fourteenth PMOS transistor is connected to a source of the thirteenth PMOS transistor;a drain of the thirteenth PMOS transistor is connected to a drain of the twelfth NMOS transistor, a source of the twelfth NMOS transistor is connected to a drain of the eleventh NMOS transistor, a source of the eleventh NMOS transistor is connected to the ground;a source of the sixteenth NMOS transistor is connected to the source of the twelfth NMOS transistor, a gate of the sixteenth NMOS transistor is connected to the drain of the twelfth NMOS transistor, a drain of the sixteenth NMOS transistor is connected to the third resistor.
  • 12. A method of amplifying, comprising:ngenerating a bias current which is independent of the power supply, so as to increase power supply rejection ratio;receiving an input voltage and generating an amplified voltage based on the biasing current;outputting a modified voltage by rectifying the amplified voltage to square wave,wherein the biasing unit comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a current mirror, a first resistor; whereina source of the first NMOS transistor is connected to a ground, a gate of the first NMOS transistor is connected to both the first resistor and a source of the second NMOS transistor, a drain of the first NMOS transistor is connected to both a gate of the second NMOS transistor and a first port of the current mirror;a drain of the second NMOS transistor is connected to a second port of the current mirror;a source of the third PMOS transistor is connected to a second voltage supply, and a drain of the third PMOS transistor is configured to output the biasing current.
    • 13. The method of claim 12, further comprisingngenerating an output voltage by buffering the modified voltage.
    • 14. The method of claim 12, whereinnthe current source comprises a fourth PMOS transistor and a fifth PMOS transistor, wherein the first port the current mirror comprises a drain of the fifth PMOS transistor, the second port of the current mirror comprises a drain of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to a gate of the fifth PMOS transistor, both sources of the fourth PMOS transistor and the fifth PMOS transistor are connected to the positive power supply.
    • 15. The method of claim 12, further comprising a sixth PMOS transistor, a first inverter and a second inverter both connected to the Schmitt trigger and configured to generate an output voltage by buffering the modified voltage, wherein a source of the sixth PMOS transistor is connected to the positive power supply, a gate of the sixth PMOS transistor is connected to the gate of the third PMOS transistor, a drain of the sixth PMOS transistor is connected to the second inverter and is configured to provide a power supply for the second inverter.
      • 16. The method of claim 15, wherein the first inverter further comprises a seventeenth MOS transistor and an eighteenth MOS transistor,nwherein a source of the seventeenth PMOS transistor is connected to the third resistor, both gates of the seventeenth PMOS transistor and the eighteenth NMOS transistor are connected to the drain of the twelfth NMOS transistor, a drain of the seventeenth PMOS transistor is connected to a drain of the eighteenth NMOS transistor, a source of the eighteenth NMOS transistor is connected to the ground.
        • 17. The method of claim 16, wherein the second inverter further comprises a nineteenth PMOS transistor and an twentieth NMOS transistor,nwherein a source of the nineteenth PMOS transistor is connected to the third resistor, both gates of the nineteenth PMOS transistor and the twentieth MOS transistor are connected to the drain of the seventeenth PMOS transistor, a drain of the nineteenth PMOS transistor is connected to a drain of the twentieth NMOS transistor, a source of the twentieth NMOS transistor is connected to the ground.
    • 18. The method of claim 12, wherein the amplifying unit comprises a seventh PMOS transistor, an eighth NMOS transistor, a first capacitor and a fifth resistor; whereinnboth gates of the seventh PMOS transistor and the eighth NMOS transistor are configured to receive an input voltage via the first capacitor; both drains of the seventh PMOS transistor and the eighth NMOS transistor are connected to the Schmitt trigger, and the source of the seventh PMOS transistor is connected to the drain of the third PMOS transistor via a second resistor, a third resistor and a fourth resistor in serials, a source of the eighth NMOS transistor is connected to the ground; wherein the fifth resistor is connected between the first capacitor and the drain of the eighth NMOS transistor.
      • 19. The method of claim 18, wherein the amplifying unit further comprises a ninth PMOS transistor, a tenth NMOS transistor, and a second capacitor, and a sixth resistor; whereinna source of the ninth PMOS transistor is connected to the source of the seventh PMOS transistor, a gate of the ninth PMOS transistor is connected to the ground via the second capacitor, a drain the ninth PMOS transistor is connected to both a gate and a drain of the tenth NMOS transistor; a source of the tenth NMOS transistor is connected to the ground; wherein the sixth resistor is connected between the second capacitor and the drain of the eighth NMOS transistor.
      • 20. The method of claim 18, wherein the Schmitt trigger comprises an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, and a fifteenth PMOS transistor,nwherein gates of all of the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth PMOS transistor and the fourteenth PMOS transistor are connected to the drain of the seventh PMOS transistor;a source of the fourteenth PMOS transistor is connected to the third resistor, a drain of the fourteenth PMOS transistor is connected to a source of the thirteenth PMOS transistor;a drain of the thirteenth PMOS transistor is connected to a drain of the twelfth NMOS transistor, a source of the twelfth NMOS transistor is connected to a drain of the eleventh NMOS transistor, a source of the eleventh NMOS transistor is connected to the ground;a source of the fifteenth PMOS transistor is connected to the source of the thirteenth PMOS transistor, a gate of the fifteenth PMOS transistor is connected to the drain of the thirteenth PMOS transistor, a drain of the fifteenth PMOS transistor is connected to the ground.
        • 21. The method of claim 20, wherein the Schmitt trigger further comprises a sixteenth NMOS transistor, whereinna source of the sixteenth NMOS transistor is connected to the source of the twelfth NMOS transistor, a gate of the sixteenth NMOS transistor is connected to the gate of the fifteenth PMOS transistor, a drain of the sixteenth NMOS transistor is connected to the third resistor.
      • 22. The method of claim 18, wherein the Schmitt trigger comprises an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, and a sixteenth NMOS transistor,nwherein gates of all of the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth PMOS transistor and the fourteenth PMOS transistor are connected to the drain of the seventh PMOS transistor;a source of the fourteenth PMOS transistor is connected to the third resistor, a drain of the fourteenth PMOS transistor is connected to a source of the thirteenth PMOS transistor;a drain of the thirteenth PMOS transistor is connected to a drain of the twelfth NMOS transistor, a source of the twelfth NMOS transistor is connected to a drain of the eleventh NMOS transistor, a source of the eleventh NMOS transistor is connected to the ground;a source of the sixteenth NMOS transistor is connected to the source of the twelfth NMOS transistor, a gate of the sixteenth NMOS transistor is connected to the drain of the twelfth NMOS transistor, a drain of the sixteenth NMOS transistor is connected to the third resistor.
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