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Patexia Research
Patent No. US 09455675
Issue Date Sep 27, 2016
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Patent 09455675 - Amplifier and amplification method > Description

Description

'\n\nCROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to Chinese Application No. 201410572751.0 entitled “amplifier and amplification method,†filed on Oct. 23, 2014 by Beken Corporation, which is incorporated herein by reference.

TECHNICAL FIELD

The present application relates to circuits, and more particularly but not exclusively to an amplifier and a method for increasing power supply rejection ratio.

BACKGROUND

The Power Supply Rejection Ratio (PSRR) is defined as the ratio of the change in supply voltage in the operational amplifier to the equivalent (differential) output voltage it produces, and is used to describe the amount of noise from a power supply that a particular device can reject. The larger the PSRR ratio, the better a circuit performs against the power noise. It is desirable to have a device and method that can increase PSRR.

SUMMARY OF THE INVENTION

In an embodiment, an amplifier comprises a biasing unit, configured to generate a bias current which is independent of the power supply, so as to increase power supply rejection ratio; an amplifying unit connected to the biasing unit and configured to receive an input voltage and generate an amplified voltage based on the biasing current; a Schmitt trigger connected to the amplifying unit and configured to generate and output a modified voltage by rectifying the amplified voltage to square wave.

In another embodiment, a method of amplifying comprises generating a bias current which is independent of the power supply, so as to increase power supply rejection ratio; receiving an input voltage and generating an amplified voltage based on the biasing current; outputting a modified voltage by rectifying the amplified voltage to square wave.

\n\n\nBRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

FIG. 1 is a diagram illustrating an embodiment of amplifier.

FIG. 2 is a diagram illustrating another embodiment of an amplifier.

FIG. 3 is a diagram illustrating an embodiment of the amplifier shown in FIG. 1.

FIG. 4 is a diagram illustrating an embodiment of the amplifier shown in FIG. 2.

FIG. 5 is a diagram illustrating another embodiment of the amplifier shown in FIG. 2.

FIG. 6 is a diagram illustrating another embodiment of the amplifier shown in FIG. 2.

FIG. 7 is an application scenario of the amplifier shown in either FIG. 1 or FIG. 2.

FIG. 8 is a flow chart of a method performed by the amplifier shown in FIG. 1.

\n\n\nDETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Various aspects and examples of the invention will now be described. The following description provides specific details for a thorough understanding and enabling description of these examples. Those skilled in the art will understand, however, that the invention may be practiced without many of these details. Additionally, some well-known structures or functions may not be shown or described in detail, so as to avoid unnecessarily obscuring the relevant description.

FIG. 1 is a diagram illustrating an amplifier 10. The amplifier 10 comprises a biasing unit 100, an amplifying unit 110, and a Schmitt trigger 120. The biasing unit 100 is configured to generate a bias current which is independent of the power supply, so as to increase power supply rejection ratio. The amplifying unit 110 is connected to the biasing unit 100 and is configured to receive an input voltage and generate an amplified voltage based on the biasing current. The Schmitt trigger 120 is connected to the amplifying unit 110, and is configured to generate and output a modified voltage by rectifying the amplified voltage to square wave.

FIG. 2 is a diagram illustrating another embodiment of an amplifier 20. A biasing unit 200, an amplifying unit 210, and a Schmitt trigger 220 are respectively similar to the biasing unit 100, the amplifying unit 110, and the Schmitt trigger 120 shown in FIG. 1, therefore details are omitted for elements already described with respect to FIG. 1. The amplifier 20 further comprises at least one inverter 230. The at least one inverter 230 is connected to the Schmitt trigger 220 and the at least one inverter 230 is configured to generate an output voltage by buffering the modified voltage. The inverter 230 further improves drive capability of the amplifier 20, so that the output current can charge a load more quickly.

FIG. 3 is a diagram illustrating an embodiment of the amplifier shown in FIG. 1. The amplifier 30 comprises a biasing unit 300, an amplifying unit 310, a Schmitt trigger 320. The biasing unit 300 comprises a first NMOS transistor M1, a second NMOS transistor M2, a third PMOS transistor M3, a current mirror 305, a first resistor R1.

A source of the first NMOS transistor M1 is connected to a ground. A gate of the first NMOS transistor M1 is connected to both the first resistor R1 and a source of the second NMOS transistor M2. The second NMOS transistor M2 operates as clamping transistor to clamp a voltage on the drain of the first NMOS transistor M1. A drain of the first NMOS transistor M1 is connected to both a gate of the second NMOS transistor M2 and a first port of the current mirror 305. The current mirror 305 is represented as a dashed block. A drain of the second NMOS transistor M2 is connected to a second port of the current mirror 305. A source of the third PMOS transistor M3 is connected to a positive voltage supply vdd. A drain of the third PMOS transistor M3 is configured to output the biasing current Iref2. The current that passes through the first resistor R1 includes a reference current Iref1. Iref1 can be represented as:

Iref⠢⠢1=(1+a+4×R⠢⠢1×Vth⠢⠢1×a2×a×R⠢⠢1)2(1)

Wherein a=0.5×un×Cox×W1/L1. W1 represents channel width of the first NMOS transistor M1. L1 represents channel length of the first NMOS transistor M1. Vth1 represents threshold of the first NMOS transistor M1. un is a constant value, and represents electron mobility. Cox represents a capacitance of a gate oxide capacitor. It can be determined from the above equation that Iref is independent of the power source vdd. Also note that Iref2=k*Iref1, therefore Iref2 is also independent of the power source vdd. As the biasing current Iref2 is independent of the power source vdd, the Power Supply Rejection Ratio can be improved with embodiments of the invention.

Alternatively, as shown in FIG. 3, the current source 305 further comprises a fourth PMOS transistor M4 and a fifth PMOS transistor M5. The first port the current mirror 305 comprises a drain of the fifth PMOS transistor M5. The second port of the current mirror 305 comprises a drain of the fourth PMOS transistor M4. The gate of the fourth PMOS transistor M4 is connected to a gate of the fifth PMOS transistor M5. Both sources of the fourth PMOS transistor M4 and the fifth PMOS transistor M5 are connected to the positive power supply vdd.

The amplifying unit 310 comprises a seventh PMOS transistor M7, an eighth NMOS transistor M8, a first capacitor C1 and a fifth resistor R5. Both gates of the seventh PMOS transistor M7 and the eighth NMOS transistor M8 are configured to receive an input voltage Vin via the first capacitor C1. Note the input voltage Vin can be provided by an oscillator not shown in FIG. 3. The first capacitor C1 is configured to provide instantaneous current to the amplifying unit 310, and further blocks the direct current. Both drains of the seventh PMOS transistor M7 and the eighth NMOS transistor M8 are connected to the Schmitt trigger 320. The source of the seventh PMOS transistor M7 is connected to the drain of the third PMOS transistor M3 via a second resistor R2, a third resistor R3 and a fourth resistor R4 in serials. A source of the eighth NMOS transistor M8 is connected to the ground. The fifth resistor R5 is connected between the first capacitor C1 and the drain of the eighth NMOS transistor M8. The fifth resistor R5 operates as a feedback resistor between drains of the seventh PMOS transistor M7 and eighth NMOS transistor M8 and gates of the seventh PMOS transistor M7 and eighth NMOS transistor Mg.

The Schmitt trigger 320 comprises an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, and a fifteenth PMOS transistor M15. Gates of all of the eleventh NMOS transistor M11, the twelfth NMOS transistor M12, the thirteenth PMOS transistor M13 and the fourteenth PMOS transistor M14 are connected to the drain of the seventh PMOS transistor M7. A source of the fourteenth PMOS transistor M14 is connected to the third resistor R3. A drain of the fourteenth PMOS transistor M14 is connected to a source of the thirteenth PMOS transistor M13. A drain of the thirteenth PMOS transistor M13 is connected to a drain of the twelfth NMOS transistor M12. A source of the twelfth NMOS transistor M12 is connected to a drain of the eleventh NMOS transistor M11. A source of the eleventh NMOS transistor M11 is connected to the ground.

A source of the fifteenth PMOS transistor M15 is connected to the source of the thirteenth PMOS transistor M13. A gate of the fifteenth PMOS transistor M15 is connected to the drain of the thirteenth PMOS transistor M13. A drain of the fifteenth PMOS transistor M15 is connected to the ground. The Schmitt trigger 320 can cancels glitch with its Hysteresis curve.

FIG. 4 is a diagram illustrating another embodiment of the amplifier shown in FIG. 2. The amplifier 40 further comprises a sixth PMOS transistor M6, a first inverter 430 and a second inverter 435. The first inverter 430 is connected to the Schmitt trigger 420, and the second inverter 435 is connected to the first inverter 430 and is configured to generate an output voltage vout by buffering the modified voltage V6.

A source of the sixth PMOS transistor M6 is connected to the positive power supply Vdd. A gate of the sixth PMOS transistor M6 is connected to the gate of the third PMOS transistor M3. A drain of the sixth PMOS transistor M6 is connected to the second inverter 435 via a second resistor R2 and is configured to provide a power supply for the second inverter 435. The sixth PMOS transistor M6 is configured to provide voltage V2′. The sixth PMOS transistor M6 is configured to provide bias voltage V2′ to the inverter stage V35 so as to improve the overall PSRR. The sixth PMOS transistor M6 has a size of K2*W/L, while the third PMOS transistor M3 has a size of K1*W/L. Further the fourth PMOS transistor M4 and the fifth PMOS transistor M5 have the same size of W/L. The transistor M3 provides bias voltage V3 to inverter 430. As the latter stage 435 has a lower power consumption relative to the preceding stage 430, K2 may be smaller than K1.

The amplifying unit 410 further comprises a ninth PMOS transistor M9, a tenth NMOS transistor M10, a second capacitor C2, and a sixth resistor R6. A source of the ninth PMOS transistor M9 is connected to the source of the seventh PMOS transistor M7. A gate of the ninth PMOS transistor M9 is connected to the ground via the second capacitor C2. A drain the ninth PMOS transistor M9 is connected to both a gate and a drain of the tenth NMOS transistor M10. A source of the tenth NMOS transistor M10 is connected to the ground. The sixth resistor R6 is connected between the second capacitor C2 and the drain of the eighth NMOS transistor Mg so as to provide a feedback path.

During operation, as the seventh PMOS transistor M7 and the ninth PMOS transistor M9 form a pair, the eighth NMOS transistor Mg and the tenth NMOS transistor M10 form a pair, they form a Pseudo-Differential input structure, which further cancels common mode voltage, therefore cancels noise from the power supply.

As shown in FIG. 4, the Schmitt trigger 420 comprises an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, and a fifteenth PMOS transistor M15. As MOS transistors M11, M12, M13 and M14 are similar to that shown in FIG. 3, details are omitted for the elements already discussed with respect to FIG. 3. The Schmitt trigger 420 further comprises a sixteenth NMOS transistor M16. A source of the sixteenth NMOS transistor M16 is connected to the source of the twelfth NMOS transistor M12. A gate of the sixteenth NMOS transistor M16 is connected to the gate of the fifteenth PMOS transistor M15. A drain of the sixteenth NMOS transistor M16 is connected the third resistor R3.

The first inverter 430 further comprises a seventeenth MOS transistor M17 and an eighteenth MOS transistor M18. A source of the seventeenth PMOS transistor M17 is connected to the third resistor R3. Both gates of the seventeenth PMOS transistor M17 and the eighteenth NMOS transistor M18 are connected to the drain of the twelfth NMOS transistor M12. A drain of the seventeenth PMOS transistor M17 is connected to a drain of the eighteenth NMOS transistor M18. A source of the eighteenth NMOS transistor M18 is connected to the ground.

In FIG. 4, the amplifier 40 further comprises a second inverter 435. The second inverter 435 further comprises a nineteenth PMOS transistor M19 and an twentieth NMOS transistor M20. A source of the nineteenth PMOS transistor M19 is connected to the second resistor R2. Both gates of the nineteenth PMOS transistor M19 and the twentieth MOS transistor M20 are connected to the drain of the seventeenth PMOS transistor M17. A drain of the nineteenth PMOS transistor M19 is connected to a drain of the twentieth NMOS transistor M20. A source of the twentieth NMOS transistor M20 is connected to the ground. Both drains of the nineteenth PMOS transistor M19 and the twentieth NMOS transistor M20 are configured to output voltage.

FIG. 5 is a diagram illustrating another embodiment of the amplifier shown in FIG. 2. The amplifier 50 comprises a biasing unit 500, an amplifying unit 510, a Schmitt trigger 520, a first inverter 530 and a second inverter 535. A biasing unit 500, an amplifying unit 510, the first inverter 530 and the second inverter 535 are respectively similar to the biasing unit 400, the amplifying unit 410, the first inverter 430 and the second inverter 435 shown in FIG. 4, therefore details are omitted for elements already described with respect to FIG. 4. The Schmitt trigger 520 comprises an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, and a sixteenth NMOS transistor M16. Gates of all of the eleventh NMOS transistor M11, the twelfth NMOS transistor M12, the thirteenth PMOS transistor M13 and the fourteenth PMOS transistor M14 are connected to the drain of the seventh PMOS transistor M7. A source of the fourteenth PMOS transistor M14 is connected to the third resistor R3. A drain of the fourteenth PMOS transistor M14 is connected to a source of the thirteenth PMOS transistor M13. A drain of the thirteenth PMOS transistor M13 is connected to a drain of the twelfth NMOS transistor M12. A source of the twelfth NMOS transistor M12 is connected to a drain of the eleventh NMOS transistor M11. A source of the eleventh NMOS transistor M11 is connected to the ground. A source of the sixteenth NMOS transistor M16 is connected to the source of the twelfth NMOS transistor M12. A gate of the sixteenth NMOS transistor M16 is connected to a drain of the twelfth NMOS transistor M12. A drain of the sixteenth NMOS transistor M16 is connected to the third resistor R3.

As shown in FIG. 5, during operation, V5 equals Vthn8+|Vthp7|, V4 equals Vthn8+|Vthp7|+Iref2×R4, V3 equals Vthn8+|Vthp7|+Iref2×(R4+R3), V2 equals Vthn8+|Vthp7|+Iref2×(R4+R3+R2). The high level voltage that V6 outputs equals Vthn8+|Vthp7|, which may be for example 1.3 v. V5 is a DC (direct current) voltage point, and V6 is the signal output point, which outputs AC (alternate current) signals. Note the high voltage level of the output AC signals equals V5. The circuit that needs to be driven by the output voltage vout requires a power of 1.8 v, which does not match the V6 output. According to an embodiment, the power supply increases step by step along the amplifying unit 510, the Schmitt trigger 520, the first inverter 530 and the second inverter 535. Therefore the output voltage vout may reach the requirement of 1.8 v. Meantime, the PSRR is not sacrificed, as the increased power supply further improves PSRR. To be specific, as the preceding stage signals are relatively smaller than the subsequent stages, preceding stages require higher PSRR than the subsequent stages. The subsequent stages have less requirement on PSRR, as the signals in the subsequent stage are amplified and less sensitive to noises. Note the higher the bias voltage, the worse the PSRR. Therefore the preceding stages require lower bias voltage, while the latter stage may have higher bias voltage, such that the overall PSRR will not be deteriorated.

FIG. 6 is a diagram illustrating another embodiment of the amplifier shown in FIG. 2. The difference between FIG. 6 and FIG. 4 lies in that the amplifier 60 comprises only one inverter 630, without the second inverter 435 shown in FIG. 4. Further in FIG. 4 it is the sixth PMOS transistor M6 that provides a power supply V2′ to the second inverter 435, while in FIG. 6, the sixth PMOS transistor M6 is omitted. As other elements in FIG. 6 are similar to that shown in FIG. 4, details are omitted for elements already discussed with respect to FIG. 4.

FIG. 7 is an application scenario of the amplifier shown in either FIG. 1 or FIG. 2. The amplifier 10 shown in FIG. 1 or FIG. 2 can be positioned between an oscillator 700 and a phase locked loop (PLL) 760. The amplifier 10 is configured to provide boosted signal to the PLL 760. The oscillator 700 may further comprise a third inverter 710, a seventh resistor 720, a crystal oscillator 730, a sixth capacitor 740 and a seventh capacitor 750. The seventh resistor 720, the sixth capacitor 740 and a seventh capacitor 750 can be configured to adjust oscillation parameter of the crystal oscillator 730.

FIG. 8 is a flow chart of a method performed by the amplifier shown in FIG. 1. The method 80 of amplifying comprises generating (in block 800) a bias current which is independent of the power supply, so as to increase power supply rejection ratio; receiving (in block 810) an input voltage and generating an amplified voltage based on the biasing current; outputting (in block 820) a modified voltage by rectifying the amplified voltage into square wave signal. Although not shown in FIG. 8, the method 80 may further comprise generating an output voltage by buffering the modified voltage with at least one inverter.

It should be appreciated by those ordinary skill in the art that components from different embodiments may be combined to yield another technical solution. This written description uses examples to disclose the invention, including the best mode, and also to enable any person ordinary skill in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those ordinary skill in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.

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