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Patexia Research
Patent No. US 10516046
Issue Date Dec 24, 2019
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Patent 10516046 - Silicon carbide semiconductor device > Claims

  • 1. A silicon carbide semiconductor device comprising: a main cell region;a sense cell region;a MOSFET arranged in each of the main cell region and the sense cell region and disposed in a semiconductor substrate which is made of silicon carbide and includes a high impurity concentration layer with a first conductivity type or a second conductivity type on a back side of the substrate and a drift layer with the first conductivity type having a lower impurity concentration than the high impurity concentration layer on a front side of the substrate;an element isolation layer arranged between the main cell region and the sense cell region, separating the main cell region and the sense cell region, and surrounding the sense cell region; anda plurality of electric field relaxation layers having the second conductivity type, arranged between the main cell region and the sense cell region, and disposed to be deeper than the element isolation layer, wherein:the MOSFET includes: a base region made of silicon carbide with the second conductivity type and arranged on the drift layer;a source region arranged on the base region, made of silicon carbide, and having the first conductivity type with a higher impurity concentration than the drift layer;a plurality of deep layers having the second conductive type with a higher impurity concentration and disposed deeper than the base region;a trench gate structure in which a gate electrode is arranged through a gate insulation film in a trench which penetrates the source region and the base region;a source electrode electrically connected to the source region and each of the deep layers; anda drain electrode electrically connected to the high impurity concentration layer;the deep layers and the electric field relaxation layers have a linear shape with one direction as a longitudinal direction, and are arranged in a stripe pattern at a predetermined interval;each of the electric field relaxation layers includes at least a first portion protruding from a main cell region side to a sense cell region side and a second portion protruding from the sense cell region side to the main cell region side;the element isolation layer is disposed deeper than the base region, and has an annular structure in which a non-overlapping region of the element isolation layer continuously surrounds the sense cell region in one turn, the non-overlapping region excluding a region of the element isolation layer overlapping with the first portion and the second portion when viewed from a normal direction to a surface of the semiconductor substrate; anda shortest distance between the first portion and the second portion is equal to or longer than a length of a depletion layer extending from the first portion and the second portion when no bias is applied and when viewed from the normal direction, and is equal to or shorter than a predetermined distance.
    • 2. The silicon carbide semiconductor device according to claim 1, wherein: the first portion and the second portion are alternately arranged by being shifted in a direction orthogonal to the longitudinal direction;the tip of the first portion is disposed between tips of the second portions; anda side of the tip of the first portion faces a side of the tip of the second portion.
    • 3. The silicon carbide semiconductor device according to claim 1, wherein: the element isolation layer includes an insulation film disposed in the trench and a polysilicon layer disposed on the insulation film; andthe insulation film arranged in the element isolation layer is thicker than a gate insulation film.
    • 4. The silicon carbide semiconductor device according to claim 1, wherein: the element isolation layer and the trench gate structure have a same depth.
  • 5. A silicon carbide semiconductor device comprising: a main cell region;a sense cell region;a MOSFET arranged in each of the main cell region and the sense cell region and disposed in a semiconductor substrate which is made of silicon carbide and includes a high impurity concentration layer with a first conductivity type or a second conductivity type on a back side of the substrate and a drift layer with the first conductivity type having a lower impurity concentration than the high impurity concentration layer on a front side of the substrate;an element isolation layer arranged between the main cell region and the sense cell region, separating the main cell region and the sense cell region, and surrounding the sense cell region; anda plurality of electric field relaxation layers having the second conductivity type, arranged between the main cell region and the sense cell region, and disposed to be deeper than the element isolation layer, wherein:the MOSFET includes: a base region made of silicon carbide with the second conductivity type and arranged on the drift layer;a source region arranged on the base region, made of silicon carbide, and having the first conductivity type with a higher impurity concentration than the drift layer;a plurality of deep layers having the second conductive type with a higher impurity concentration and disposed deeper than the base region;a trench gate structure in which a gate electrode is arranged through a gate insulation film in a trench which penetrates the source region and the base region;a source electrode electrically connected to the source region and each of the deep layers; anda drain electrode electrically connected to the high impurity concentration layer;the deep layers and the electric field relaxation layers have a linear shape with one direction as a longitudinal direction, and are arranged in a stripe pattern at a predetermined interval;each of the electric field relaxation layers includes at least a first portion protruding from a main cell region side to a sense cell region side and a second portion protruding from the sense cell region side to the main cell region side;the element isolation layer is disposed deeper than the base region, and includes a pair of two sides passing between a tip of the first portion and a tip of the second portion or passing through both tips, respectively, and another pair of two sides arranged along the longitudinal direction of the deep layers and the electric field relaxation layers, the other pair of two sides being different from the pair of two sides; anda shortest distance between the first portion and the second portion is equal to or longer than a length of a depletion layer extending from the first portion and the second portion when no bias is applied, and is equal to or less than a predetermined distance.
    • 6. The silicon carbide semiconductor device according to claim 5, wherein: a width of each of the other pair of two sides in the element isolation layer is wider than a predetermined distance.
    • 7. The silicon carbide semiconductor device according to claim 5, wherein: the tip of the first portion and the tip of the second portion are opposed to each other, and the shortest distance is defined as a distance between the tips; anda width of each of the pair of two sides in the element isolation layer is longer than the shortest distance, and the tip of the first portion and the tip of the second portion are disposed at a bottom of each of the pair of two sides.
      • 8. The silicon carbide semiconductor device according to claim 7, wherein: the electric field relaxation layers are defined as first electric field relaxation layers,the silicon carbide semiconductor device further comprising:a second electric field relaxation layer having the second conductivity type and disposed at a position corresponding to a space between the first portion and the second portion, which is a space between adjacent first electric field relaxation layers arranged at the predetermined interval.
    • 9. The silicon carbide semiconductor device according to claim 5, wherein: the first portion and the second portion are alternately arranged by being shifted in a direction orthogonal to the longitudinal direction;the tip of the first portion is disposed between tips of the second portions; anda side of the tip of the first portion faces a side of the tip of the second portion.
    • 10. The silicon carbide semiconductor device according to claim 5, wherein: the element isolation layer includes an insulation film disposed in the trench and a polysilicon layer disposed on the insulation film; andthe insulation film arranged in the element isolation layer is thicker than a gate insulation film.
    • 11. The silicon carbide semiconductor device according to claim 5, wherein: the element isolation layer and the trench gate structure have a same depth.
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