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Patexia Research
Patent No. US 11057035
Issue Date Jul 6, 2021
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Patent 11057035 - Multi-voltage input output device > Claims

  • 1. A semiconductor device having a pull up network comprising: a first transistor having a first gate coupled to a first bias voltage;a second transistor having a second gate coupled to a first gate signal that varies between the first bias voltage and a first source voltage; anda switch network responsive to an input control signal for selectably providing as the first bias voltage one of a plurality of available voltages, the switch network having a buffer that is responsive to the input control signal for selectively providing as the first bias voltage one of a second bias voltage, a second source voltage, and a third voltage between the second bias voltage and the second source voltage.
    • 2. The semiconductor device of claim 1 having a pull down network including: a third transistor having a third gate coupled to the second bias voltage; anda fourth transistor having a fourth gate coupled to a second gate signal that varies between the second source voltage and the second bias voltage, wherein the pull up network is configured such that, when the first gate signal takes the first source voltage, the second transistor takes the second bias voltage, and the third transistor is on and the fourth transistor is on and the output voltage is the second source voltage.
      • 3. The semiconductor device of claim 2, wherein: the first source voltage is nominally 3.3 volts, the second source voltage is nominally 0.0 volts, and both the first bias voltage and the second bias voltage are nominally 1.8 volts; orwherein the first source voltage is nominally 2.5 volts, the second source voltage is nominally 0.0 volts, and the first bias voltage is nominally 0.8 volts and the second bias voltage is nominally 1.8 volts; orwherein the first source voltage is nominally 1.8 volts, the second source voltage is nominally 0.0 volts, and the first bias voltage is nominally 0.0 volts, and the second bias voltage is nominally 1.8 volts.
    • 4. The semiconductor device of claim 1, wherein the pull up network is configured such that, when the first gate signal takes the first bias voltage, the first transistor is on.
    • 5. The semiconductor device of claim 1, wherein the first and second transistors are p-type finFET and the third and fourth transistors are n-type finFETs each having a same nominal maximum voltage.
      • 6. The semiconductor device of claim 5, wherein the nominal maximum voltage is 1.98 volts.
  • 7. A semiconductor device for signaling at an output comprising: a first tracking circuit, wherein the first tracking circuit is configured to providea first varying voltage, the first varying voltage varying between a bias voltage and an output voltage present at an output, further wherein first, second and third transistors are coupled in series between the output and a variable power source such that when a first gate signal takes the bias voltage the first transistor is on and the output voltage takes high output voltage;a transmission circuit capable of transmitting a transmission signal comprising the high output voltage and a low output voltage and having a plurality of different configurations; anda buffer selectively providing an input signal to one of the plurality of different configurations of the transmission circuit;wherein: the first gate signal and the second gate signal are derived from the input signal.
    • 8. The semiconductor device of claim 7, further comprising a bias voltage generator including: a first switch coupled between a first bias voltage and the bias voltage line;a second switch coupled between a second bias voltage and the bias voltage line;a third switch coupled between a third bias voltage and the bias voltage line; anda control circuit for selectively closing one or more of the first switch, the second switch and the third switch, thereby providing one of the first bias voltage, the second bias voltage, or the third bias voltage to the bias voltage line as the bias voltage.
      • 9. The semiconductor device of claim 8, further comprising a second power source providing a low output voltage; a fourth transistor having a fourth gate coupled to a second tracking circuit;a fifth transistor having a fifth gate coupled to the first bias voltage;a sixth transistor having a sixth gate coupled to a second gate signal that varies between the low output voltage and the first bias voltage, wherein the second tracking circuit is configured to provide a second varying voltage to the fourth gate, the second varying voltage varying between the first bias voltage and the output voltage, further wherein the fourth, fifth, and sixth transistors are coupled in series between the output and the second power source, such that when the first gate signal takes the high output voltage the first transistor is off, the second gate signal takes first bias voltage, and the output voltage takes the low output voltage.
        • 10. The semiconductor device of claim 9, wherein: the first voltage is nominally 3.3 volts, the second voltage is nominally 2.5 volts, the third voltage is nominally 1.8 volts, the low output voltage is nominally 0.0 volts, the first bias voltage is nominally 1.8 volts, the second bias voltage is nominally 0.8 volts and, and the third bias voltage is nominally 0.0 volts; and further wherein, when the variable power supply is selectively providing the first voltage, the first switch is closed thereby providing the first bias voltage to the bias voltage line and the bias voltage is the first bias voltage.
    • 11. The semiconductor device of claim 7, wherein at least one of the first, second, third, fourth, fifth, or sixth transistors is a finFETs having a VMAX less than the high output voltage.
      • 12. The semiconductor device of claim 11, wherein the finFET is formed by a 7 nm, 10 nm, or 16 nm process.
    • 13. The semiconductor device of claim 7, wherein a transistor gate pitch between any two transistors of the semiconductor device is 56 nanometers or less and an interconnection pitch between any two interconnection lines of the device is 40 nanometers or less.
    • 14. The semiconductor device of claim 7 further comprising a transmission circuit, the transmission circuit being capable of transmitting a transmission signal, the transmission signal comprising the high output voltage and the low output voltage, the transmission circuit comprising a buffer, the buffer being configured for providing an input signal, wherein the first gate signal and the second gate signal are derived from the input signal, wherein the transmission signal varies with the output voltage at the output.
      • 15. The semiconductor device of claim 14, wherein the transmission circuit is a member of a system on a chip.
  • 16. A method of transmitting a signal, comprising: applying a first gate signal to a first transistor gate for gating a transmit high voltage to an output path through source and drain terminals of a first transistor;generating a bias voltage using a switch network having a buffer that is responsive to an input control signal for selectively providing as the bias voltage one of a second bias voltage, a second source voltage, and a third voltage between the second bias voltage and the second source voltage andselectively applying the bias voltage to a second transistor gate of the second transistor.
    • 17. The method of claim 16, wherein the second transistor is formed from one of a 7 nm, a 10 nm, or a 16 nm process.
      • 18. The method of claim 17, further comprising selectively applying, as the transmit high voltage, 1.8 volts nominal, 2.5 volts nominal, or 3.3 volts nominal to the source or drain terminal of the first transistor, the first transistor and the second transistor being fin-type field effect transistors (finFET).
    • 19. The method of claim 16, wherein the maximum rated voltage of the second transistor is nominally 1.98 volts.
      • 20. The method of claim 19, wherein when applying nominal 1.8 volts as the transmit high voltage, the generated bias voltage is nominally 0 volts; and when applying nominal 2.5 volts as the transmit high voltage, the generated bias voltage is nominally 0.8 volts; and when applying nominal 3.3 volts as the transmit high voltage, the generated bias voltage is nominally 1.8 volts.
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