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Patexia Research
Patent No. US 11115038
Issue Date Sep 7, 2021
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Patent 11115038 - Method for managing the startup of a phase-locked loop and corresponding integrated circuit > Claims

  • 1. A method for operating a phase-locked loop (PLL) circuit, comprising: delivering a reference signal for a phase comparator of the PLL circuit;resetting a first divider of an output signal of a voltage-controlled oscillator of the PLL circuit at each first type signal edge of the reference signal;outputting by the phase comparator, in response to the reference signal and a feedback signal derived from an output of said first divider, a control pulse at each second type signal edge of the reference signal; andduring startup, increasing a control voltage of the voltage-controlled oscillator in response to each control pulse by applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator;after startup is complete, ceasing to apply the pre-charging current to the resistive capacitive filter in response to each control pulse.
    • 2. The method according to claim 1, wherein delivering said reference signal comprises dividing an initial reference signal by two, and wherein said feedback signal is the output of the first divider divided by two.
    • 4. The method according to claim 1, further comprising terminating startup when a duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.
      • 5. The method according to claim 4, further comprising, in response to terminating startup, connecting the output of the phase comparator to a charge pump circuit configured to generate the control voltage of the voltage-controlled oscillator.
        • 6. The method according to claim 5, further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.
      • 7. The method according to claim 4, wherein delivering said reference signal comprises dividing an initial reference signal by two, and wherein said feedback signal is the output of the first divider divided by two, and further comprising, in response to terminating startup, delivering the initial reference signal to the phase comparator, and delivering the output signal of the first divider as the feedback signal to the phase comparator.
        • 8. The method according to claim 7, further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.
  • 3. A method for operating a phase-locked loop (PLL) circuit, comprising: delivering a reference signal for a phase comparator of the PLL circuit;resetting a first divider of an output signal of a voltage-controlled oscillator of the PLL circuit at each first type signal edge of the reference signal;outputting by the phase comparator, in response to the reference signal and a feedback signal derived from an output of said first divider, a control pulse at each second type signal edge of the reference signal; andincreasing a control voltage of the voltage-controlled oscillator in response to each control pulse;wherein increasing the control voltage of the voltage-controlled oscillator comprises applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator;wherein the resistive capacitive filter comprises: a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the voltage-controlled oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; anda second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance;the first capacitance being equal to a value that is A times the second capacitance, and the first resistance being equal to a value that is A times the second resistance; andwherein said pre-charging current is applied to said intermediate node.
    • 19. The method according to claim 3, further comprising terminating startup when a duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.
      • 20. The method according to claim 19, further comprising, in response to terminating startup, connecting the output of the phase comparator to a charge pump circuit configured to generate the control voltage of the voltage-controlled oscillator.
        • 21. The method according to claim 20, further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.
      • 22. The method according to claim 19, wherein delivering said reference signal comprises dividing an initial reference signal by two, and wherein said feedback signal is the output of the first divider divided by two, and further comprising, in response to terminating startup, delivering the initial reference signal to the phase comparator, and delivering the output signal of the first divider as the feedback signal to the phase comparator.
        • 23. The method according to claim 22, further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.
  • 9. A phase-locked loop (PLL) circuit, comprising: a phase comparator;a voltage-controlled oscillator;a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator;a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator;a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal;wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; anda control circuit configured to: during the startup phase, increase a control voltage of the voltage-controlled oscillator during said control pulse by applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator, butafter the startup phase is complete, ceasing to apply the pre-charging current to the resistive capacitive filter in response to each pulse.
    • 31. The circuit according to claim 9, wherein the delivery circuit comprises: an input configured to receiving an initial reference signal;a divide-by-two divider connected to said input; andan output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, andfurther comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator.
    • 32. The circuit according to claim 9, wherein the resistive capacitive filter comprises: a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; anda second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance;wherein the first capacitance is equal to a value A times the second capacitance, and wherein the first resistance is equal to a value A times the second resistance; andwherein a current source is connected to said intermediate node to deliver the pre-charge current.
    • 33. The circuit according to claim 9, further comprising a detection circuit configured to detect an end of the startup phase.
      • 34. The circuit according to claim 33, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator in order to detect end of the startup phase.
        • 35. The circuit according to claim 34, wherein the detection circuit is further configured generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.
      • 36. The circuit according to claim 33, further comprising a switching circuit configured, when the startup phase has ended, to connect the output of the phase comparator to a charge pump circuit which generates the control voltage of the voltage-controlled oscillator.
        • 37. The circuit according to claim 36, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.
      • 38. The circuit according to claim 33, wherein the delivery circuit comprises: an input configured to receiving an initial reference signal;a divide-by-two divider connected to said input; andan output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, andfurther comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator;wherein the delivery circuit is configured, when the startup phase has ended, to deliver the initial reference signal to the phase comparator;a control circuit configured to deactivate said other divide-by-two divider, such that a feedback signal delivered to the phase comparator is the output signal of the first divider.
        • 39. The circuit according to claim 38, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.
  • 10. A phase-locked loop (PLL) circuit, comprising: a phase comparator;a voltage-controlled oscillator;a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator;a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator;a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal;wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; anda control circuit configured to increase a control voltage of the voltage-controlled oscillator during said control pulse;wherein the delivery circuit comprises: an input configured to receiving an initial reference signal;a divide-by-two divider connected to said input; andan output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, andanother divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator.
    • 40. The circuit according to claim 10, wherein the control circuit comprises: a current source configured to generate a pre-charging current that is selectively applied, in response to said control pulse, to a resistive capacitive filter connected at the input of the voltage-controlled oscillator.
      • 41. The circuit according to claim 40, wherein the resistive capacitive filter comprises: a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; anda second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance;wherein the first capacitance is equal to a value A times the second capacitance, and wherein the first resistance is equal to a value A times the second resistance; andwherein the current source is connected to said intermediate node.
    • 42. The circuit according to claim 10, further comprising a detection circuit configured to detect an end of the startup phase.
      • 43. The circuit according to claim 42, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator in order to detect end of the startup phase.
        • 44. The circuit according to claim 43, wherein the detection circuit is further configured generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.
      • 45. The circuit according to claim 42, further comprising a switching circuit configured, when the startup phase has ended, to connect the output of the phase comparator to a charge pump circuit which generates the control voltage of the voltage-controlled oscillator.
        • 46. The circuit according to claim 45, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.
      • 47. The circuit according to claim 42, wherein the delivery circuit comprises: an input configured to receiving an initial reference signal;a divide-by-two divider connected to said input; andan output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, andfurther comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator;wherein the delivery circuit is configured, when the startup phase has ended, to deliver the initial reference signal to the phase comparator;a control circuit configured to deactivate said other divide-by-two divider, such that a feedback signal delivered to the phase comparator is the output signal of the first divider.
        • 48. The circuit according to claim 47, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.
  • 11. A phase-locked loop (PLL) circuit, comprising: a phase comparator;a voltage-controlled oscillator;a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator;a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator;a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal;wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; anda control circuit configured to increase a control voltage of the voltage-controlled oscillator during said control pulse;wherein the control circuit comprises: a current source configured to generate a pre-charging current that is selectively applied, in response to said control pulse, to a resistive capacitive filter connected at the input of the voltage-controlled oscillator;wherein the resistive capacitive filter comprises: a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; anda second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance;wherein the first capacitance is equal to a value A times the second capacitance, and wherein the first resistance is equal to a value A times the second resistance; andwherein the current source is connected to said intermediate node.
    • 24. The circuit according to claim 11, further comprising a detection circuit configured to detect an end of the startup phase.
      • 25. The circuit according to claim 24, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator in order to detect end of the startup phase.
        • 26. The circuit according to claim 25, wherein the detection circuit is further configured generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.
      • 27. The circuit according to claim 24, further comprising a switching circuit configured, when the startup phase has ended, to connect the output of the phase comparator to a charge pump circuit which generates the control voltage of the voltage-controlled oscillator.
        • 28. The circuit according to claim 27, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.
      • 29. The circuit according to claim 24, wherein the delivery circuit comprises: an input configured to receiving an initial reference signal;a divide-by-two divider connected to said input; andan output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, andfurther comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator;wherein the delivery circuit is configured, when the startup phase has ended, to deliver the initial reference signal to the phase comparator;a control circuit configured to deactivate said other divide-by-two divider, such that a feedback signal delivered to the phase comparator is the output signal of the first divider.
        • 30. The circuit according to claim 29, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.
  • 12. A phase-locked loop (PLL) circuit, comprising: a phase comparator;a voltage-controlled oscillator;a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator;a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator;a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal;wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal;a control circuit configured to increase a control voltage of the voltage-controlled oscillator during said control pulse; anda detection circuit configured to detect an end of the startup phase.
    • 13. The circuit according to claim 12, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator in order to detect end of the startup phase.
      • 14. The circuit according to claim 13, wherein the detection circuit is further configured generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.
    • 15. The circuit according to claim 12, further comprising a switching circuit configured, when the startup phase has ended, to connect the output of the phase comparator to a charge pump circuit which generates the control voltage of the voltage-controlled oscillator.
      • 16. The circuit according to claim 15, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.
    • 17. The circuit according to claim 12, wherein the delivery circuit comprises: an input configured to receiving an initial reference signal;a divide-by-two divider connected to said input; andan output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, andfurther comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator;wherein the delivery circuit is configured, when the startup phase has ended, to deliver the initial reference signal to the phase comparator;a control circuit configured to deactivate said other divide-by-two divider, such that a feedback signal delivered to the phase comparator is the output signal of the first divider.
      • 18. The circuit according to claim 17, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.
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