Search
Patexia Research
Patent No. US 11296665
Issue Date Apr 5, 2022
Claim this patent
PDF Unavailable

Patent 11296665 - Amplifier arrangement > Claims

  • 1. An amplifier arrangement comprising an input (IN) with a capacitor (Cin) for connecting to an analog input audio signal, whereby the input audio signal is converted into an audio signal with a predetermined DC voltage component (Vk);a first amplifier branch which has a first gain factor (G1) and which receives the audio signal with the predetermined DC voltage component (Vk) as input signal, the first amplifier branch being DC coupled and outputting a first output voltage (VOUT1);a second amplifier branch which has a second gain factor (G2) and which also receives the audio signal with the predetermined DC voltage component (Vk) as input signal, the second amplifier branch being DC coupled and outputting a second output voltage (VOUT2), wherein the second gain factor (G2) is lower than the first gain factor (G1); anda differentiating member (D) for generating a voltage difference between the first output voltage (VOUT1) and the second output voltage (VOUT2), wherein a control voltage (Vbias) for setting the predetermined DC voltage component (Vk) of the input signal is obtained from the voltage difference such that a DC component of the voltage difference is minimized.
    • 2. The amplifier arrangement according to claim 1, further comprising an integrating member (INT) configured for integrating DC components of the voltage difference over time, wherein an output signal of the integrating member is said control voltage (Vbias).
      • 3. The amplifier arrangement according to claim 2, wherein a closed control loop is created by feeding back the control voltage (Vbias) to the input signal, and wherein the integrator (INT) is adapted for the closed control loop to have a cutoff frequency of 5 Hz or less.
      • 4. The amplifier arrangement according to claim 2, further comprising at least one low-pass element (RfbCfb) connected to an output of the differentiating member (D) to filter said voltage difference provided by the differentiating member (D), wherein a low-pass filtered voltage difference between the first output voltage (VOUT1) and the second output voltage (VOUT2) is generated that comprises said DC components of the voltage difference that the integrating member (INT) integrates.
    • 5. The amplifier arrangement according to claim 1, further comprising at least two low-pass elements (R8C2, R6C4), wherein the at least two low-pass elements are connected to two inputs of the differentiating member (D) to filter the first output voltage (VOUT1) and the second output voltage (VOUT2) before being input to the differentiating member.
    • 6. The amplifier arrangement according to claim 1, wherein the second gain factor (G2) is at least ten times less than the first gain factor (G1).
    • 7. The amplifier arrangement according to claim 1, wherein the first amplifier branch comprises at least one discrete low-noise transistor as an amplifying element.
    • 8. The amplifier arrangement according to claim 1, wherein the second amplifier branch comprises at least one operational amplifier as an amplifying element.
    • 9. The amplifier arrangement according to claim 1, further comprising a control input for applying a control voltage (Vref) that controls a DC component of the first and second output voltages (VOUT1, VOUT2).
    • 10. The amplifier arrangement according to claim 1, wherein the DC component of the voltage difference is minimized to be substantially zero.
    • 11. The amplifier arrangement according to claim 1, further comprising a first analog-to-digital converter that is DC coupled to the output (OUT1) of the first amplifier branch and that converts the first output voltage (VOUT1) into a digital value; anda second analog-to-digital converter that is DC coupled to the output (OUT2) of the second amplifier branch and that converts the second output voltage (VOUT2) into a digital value.
      • 12. The amplifier arrangement according to claim 11, further comprising a software configured processing unit and a switch, the software configured processing unit (HP1,HP2,G2/G1) being configured for normalizing at least one of the first and second digital values and for compensating the first amplification factor (G1), and the switch being configured for automatically switching between the normalized first digital value and the normalized second digital value, wherein either the normalized first or second digital value is provided at an output (OUT) of the amplifier arrangement.
    • 13. A wireless microphone comprising an amplifier arrangement according to claim 1.
    • 14. A pocket transmitter or mobile radio comprising an amplifier arrangement according to claim 1.
Menu