Wayne A Langel
Examiner (ID: 2393, Phone: (571)272-1353 , Office: P/1736 )
Most Active Art Unit | 1103 |
Art Unit(s) | 1754, 1793, 1103, 1206, 2899, 1736 |
Total Applications | 4779 |
Issued Applications | 3693 |
Pending Applications | 335 |
Abandoned Applications | 548 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4104872
[patent_doc_number] => 06049227
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'FPGA with a plurality of I/O voltage levels'
[patent_app_type] => 1
[patent_app_number] => 9/187666
[patent_app_country] => US
[patent_app_date] => 1998-11-05
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/049/06049227.pdf
[firstpage_image] =>[orig_patent_app_number] => 187666
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/187666 | FPGA with a plurality of I/O voltage levels | Nov 4, 1998 | Issued |
Array
(
[id] => 3933962
[patent_doc_number] => 05952845
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Semiconductor programmable test arrangement such as an antifuse ID circuit having common access switches and/or common programming switches'
[patent_app_type] => 1
[patent_app_number] => 9/144807
[patent_app_country] => US
[patent_app_date] => 1998-09-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/952/05952845.pdf
[firstpage_image] =>[orig_patent_app_number] => 144807
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/144807 | Semiconductor programmable test arrangement such as an antifuse ID circuit having common access switches and/or common programming switches | Aug 31, 1998 | Issued |
Array
(
[id] => 4163644
[patent_doc_number] => 06104209
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-15
[patent_title] => 'Low skew differential receiver with disable feature'
[patent_app_type] => 1
[patent_app_number] => 9/140857
[patent_app_country] => US
[patent_app_date] => 1998-08-27
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[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/104/06104209.pdf
[firstpage_image] =>[orig_patent_app_number] => 140857
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/140857 | Low skew differential receiver with disable feature | Aug 26, 1998 | Issued |
Array
(
[id] => 4213998
[patent_doc_number] => 06028446
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Flexible synchronous and asynchronous circuits for a very high density programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 9/118200
[patent_app_country] => US
[patent_app_date] => 1998-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
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[firstpage_image] =>[orig_patent_app_number] => 118200
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/118200 | Flexible synchronous and asynchronous circuits for a very high density programmable logic device | Jul 16, 1998 | Issued |
Array
(
[id] => 3931284
[patent_doc_number] => 05945845
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Method and apparatus for enhanced booting and DC conditions'
[patent_app_type] => 1
[patent_app_number] => 9/112905
[patent_app_country] => US
[patent_app_date] => 1998-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/945/05945845.pdf
[firstpage_image] =>[orig_patent_app_number] => 112905
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/112905 | Method and apparatus for enhanced booting and DC conditions | Jul 8, 1998 | Issued |
09/104465 | COMPOSABLE MEMORY ARRAY FOR A PROGRAMMABLE LOGIC DEVICE AND METHOD FOR IMPLEMENTING SAME | Jun 24, 1998 | Issued |
Array
(
[id] => 4413198
[patent_doc_number] => 06172517
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'Signal transmitting device, circuit block and integrated circuit suited to fast signal transmission'
[patent_app_type] => 1
[patent_app_number] => 9/084017
[patent_app_country] => US
[patent_app_date] => 1998-05-26
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[pdf_file] => patents/06/172/06172517.pdf
[firstpage_image] =>[orig_patent_app_number] => 084017
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/084017 | Signal transmitting device, circuit block and integrated circuit suited to fast signal transmission | May 25, 1998 | Issued |
Array
(
[id] => 4245684
[patent_doc_number] => 06081133
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Universal receiver device'
[patent_app_type] => 1
[patent_app_number] => 9/073958
[patent_app_country] => US
[patent_app_date] => 1998-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 4839
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[pdf_file] => patents/06/081/06081133.pdf
[firstpage_image] =>[orig_patent_app_number] => 073958
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/073958 | Universal receiver device | May 6, 1998 | Issued |
Array
(
[id] => 4023186
[patent_doc_number] => 05907248
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-25
[patent_title] => 'FPGA interconnect structure with high-speed high fanout capability'
[patent_app_type] => 1
[patent_app_number] => 9/020369
[patent_app_country] => US
[patent_app_date] => 1998-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 13847
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/907/05907248.pdf
[firstpage_image] =>[orig_patent_app_number] => 020369
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/020369 | FPGA interconnect structure with high-speed high fanout capability | Feb 8, 1998 | Issued |
Array
(
[id] => 4040487
[patent_doc_number] => 05994921
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Universal sender device'
[patent_app_type] => 1
[patent_app_number] => 9/015549
[patent_app_country] => US
[patent_app_date] => 1998-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/994/05994921.pdf
[firstpage_image] =>[orig_patent_app_number] => 015549
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/015549 | Universal sender device | Jan 28, 1998 | Issued |
Array
(
[id] => 3919875
[patent_doc_number] => 06002269
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'TTL logic driver circuit'
[patent_app_type] => 1
[patent_app_number] => 8/996866
[patent_app_country] => US
[patent_app_date] => 1997-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/002/06002269.pdf
[firstpage_image] =>[orig_patent_app_number] => 996866
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/996866 | TTL logic driver circuit | Dec 22, 1997 | Issued |
Array
(
[id] => 4149656
[patent_doc_number] => 06031390
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Asynchronous registers with embedded acknowledge collection'
[patent_app_type] => 1
[patent_app_number] => 8/991141
[patent_app_country] => US
[patent_app_date] => 1997-12-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/031/06031390.pdf
[firstpage_image] =>[orig_patent_app_number] => 991141
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/991141 | Asynchronous registers with embedded acknowledge collection | Dec 15, 1997 | Issued |
Array
(
[id] => 4186521
[patent_doc_number] => 06037803
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Integrated circuit having two modes of I/O pad termination'
[patent_app_type] => 1
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[pdf_file] => patents/06/037/06037803.pdf
[firstpage_image] =>[orig_patent_app_number] => 990060
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/990060 | Integrated circuit having two modes of I/O pad termination | Dec 11, 1997 | Issued |
Array
(
[id] => 4226218
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[patent_title] => 'Method for providing two modes of I/O pad termination'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/990057 | Method for providing two modes of I/O pad termination | Dec 11, 1997 | Issued |
Array
(
[id] => 4005151
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[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Programmable application specific integrated circuit and logic cell therefor'
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[firstpage_image] =>[orig_patent_app_number] => 988432
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/988432 | Programmable application specific integrated circuit and logic cell therefor | Dec 10, 1997 | Issued |
Array
(
[id] => 3946394
[patent_doc_number] => 05973512
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'CMOS output buffer having load independent slewing'
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[pdf_file] => patents/05/973/05973512.pdf
[firstpage_image] =>[orig_patent_app_number] => 982959
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/982959 | CMOS output buffer having load independent slewing | Dec 1, 1997 | Issued |
Array
(
[id] => 4077492
[patent_doc_number] => 06069493
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-30
[patent_title] => 'Input circuit and method for protecting the input circuit'
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[pdf_file] => patents/06/069/06069493.pdf
[firstpage_image] =>[orig_patent_app_number] => 980250
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/980250 | Input circuit and method for protecting the input circuit | Nov 27, 1997 | Issued |
Array
(
[id] => 3991116
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[patent_kind] => NA
[patent_issue_date] => 1999-06-08
[patent_title] => 'Method and system for layout and schematic generation for heterogeneous arrays'
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[pdf_file] => patents/05/910/05910733.pdf
[firstpage_image] =>[orig_patent_app_number] => 968543
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/968543 | Method and system for layout and schematic generation for heterogeneous arrays | Nov 11, 1997 | Issued |
Array
(
[id] => 3803773
[patent_doc_number] => 05828232
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Circuit to reduce current and voltage spikes when switching inductive loads'
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[firstpage_image] =>[orig_patent_app_number] => 966594
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/966594 | Circuit to reduce current and voltage spikes when switching inductive loads | Nov 9, 1997 | Issued |
Array
(
[id] => 3812942
[patent_doc_number] => 05854561
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-29
[patent_title] => 'Switched substrate bias for MOS DRAM circuits'
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[patent_app_country] => US
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[pdf_file] => patents/05/854/05854561.pdf
[firstpage_image] =>[orig_patent_app_number] => 957426
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/957426 | Switched substrate bias for MOS DRAM circuits | Oct 23, 1997 | Issued |