Method and system for reducing inter-layer capacitance in integrated circuits | Patent Number 07396760

US 07396760 B2
Application Number10991107
Publication NumberUS 20060105564 A1
Pendency3 years, 7 months, 24 days
Filled DateNov 17, 2004
Priority DateNov 17, 2004
Publication DateMay 18, 2006
Expiration DateNov 17, 2024
Inventor/ApplicantsKunal N. Taravade
Neal Callan
Paul G. Filseth
ExaminesPICARDAT, KEVIN M
Art Unit2822
Technology Center2800
Assignments
Hilco Patent Acquisition 55 Llc
Current
Bell Semiconductor Llc
Current
Bellnorthern Research
Current
Lsi BroadcomBroadcom
Original
Law Firm
You must be logged in to view
Login
Attorneys
Subscription-Only
View Concierge Program
Patent Prosecution report image

Empower your practice with Patexia Publication Prosecution IP Module.

Get access to our exclusive rankings and unlock powerful data.
Check our Latest ReportPurchase IP Module

Looking for a Publication Attorney?

Get in touch with our team or create your account to start exploring a network of over 120K attorneys.