Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect | Patent Publication Number 20020106886

US 20020106886 A1
Patent NumberUS 06849946 B2
Application Number9779123
Filled DateFeb 7, 2001
Priority DateAug 31, 1998
Publication DateAug 8, 2002
Original AssigneeInfineon Technologies Ag
Current AssigneePhorus Inc.
Ibiquity Digital Corporation
Tessera Advanced Technologies Inc.
Dts
Tessera Xperi
Invensas Corporation
Inventor/ApplicantsChristopher A. Seams
Anantha R. Sethuraman
Anantha R. Sethuraman
Christopher A. Seams
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