Method for providing clock-net aware dummy metal using dummy regions | Patent Publication Number 20050028121

US 20050028121 A1

Patent NumberUS 07007259 B2

Application Number10632622

Filled DateJul 31, 2003

Priority DateJul 31, 2003

Publication DateFeb 3, 2005

Original AssigneeLsi Logic Corporation

Current AssigneeHilco Patent Acquisition 55 Llc
Bellnorthern Research
Bell Semiconductor Llc

Inventor/ApplicantsSanthanakrishnan Raman
Vikram Shrowty

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