Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses | Patent Application Number 10871825
10871825
Not Appealed
Inventor/ApplicantsJoseph Tzou
Thinh Tran
Suresh Parameswaran
Thinh Tran
Suresh Parameswaran
ExaminesNGUYEN, NAM THANH
Art Unit2824
Technology Center2800
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