Integrated circuit and associated layout with gate electrode level portion including at least two complimentary transistor forming linear conductive segments and at least one non-gate linear conductive segment | Patent Number 07943966

US 07943966 B2
Application Number12561229
Publication NumberUS 20100011327 A1
Pendency1 year, 8 months, 3 days
Filled DateSep 16, 2009
Priority DateMar 9, 2006
Publication DateJan 14, 2010
Expiration DateMay 17, 2023
Inventor/ApplicantsMichael C. Smayling
Scott T. Becker
ExaminesHOANG, QUOC DINH
Art Unit2892
Technology Center2800
Assignments
Avidbank Corporate Finance
Current
Tela Innovations Inc.Emerald Innovations
Original
Rpx Corporation
Original
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