Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip | Patent Application Number 11652302
11652302
Not Appealed
Patent NumberUS 07546567 B2
Publication NumberUS 20080168412 A1
Filled DateJan 10, 2007
Priority DateJan 10, 2007
Inventor/ApplicantsPei-Hsin Ho
Yongseok Cheon
Yongseok Cheon
ExaminesGARBOWSKI, LEIGH M
Art Unit2825
Technology Center2800
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