Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip | Patent Number 07546567

US 07546567 B2
Application Number11652302
Publication NumberUS 20080168412 A1
Pendency2 years, 5 months, 1 day
Filled DateJan 10, 2007
Priority DateJan 10, 2007
Publication DateJul 10, 2008
Expiration DateJan 9, 2027
Inventor/ApplicantsPei-Hsin Ho
Yongseok Cheon
ExaminesGARBOWSKI, LEIGH M
Art Unit2825
Technology Center2800
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